Searched refs:SHA1 (Results 1 – 16 of 16) sorted by relevance
76 bool "Enable optional SHA1 hmac cookie generation"78 Enable optional SHA1 hmac based SCTP cookie generation96 bool "Enable optional SHA1 hmac cookie generation"98 Enable optional SHA1 hmac based SCTP cookie generation
27 SHA164 SHA1
22 #define SHA1 \ macro
39 tristate "PadLock driver for SHA1 and SHA256 algorithms"45 Use VIA PadLock for SHA1/SHA256 algorithms.80 tristate "SHA1 digest algorithm"280 tristate "Support for OMAP MD5/SHA1/SHA2 hw accelerator"288 OMAP processors have MD5/SHA1/SHA2 hw accelerator. Select this if you289 want to use the OMAP module for MD5/SHA1/SHA2 algorithms.411 Some Atmel processors have SHA1/SHA224/SHA256/SHA384/SHA512414 SHA1/SHA224/SHA256/SHA384/SHA512 algorithms.440 The Freescale i.MX23/i.MX28 has SHA1/SHA256 and AES128 CBC/ECB481 hardware hash accelerator. Supporting MD5/SHA1/SHA224/SHA256[all …]
12 tristate "SHA1 digest algorithm (ARM-asm)"20 tristate "SHA1 digest algorithm (ARM NEON)"31 tristate "SHA1 digest algorithm (ARM v8 Crypto Extensions)"
4 SHA1, SHA224, SHA256 and MD5 hashes
113 module_cpu_feature_match(SHA1, sha1_ce_mod_init);
34 bool "SHA1 hash of loaded profiles"
62 calculated with the SHA1 or MD5 hash algorithm;66 prefix is shown only if the hash algorithm is not SHA1 or MD5);
78 [HASH_ALGO_SHA1] = _(SHA1),
40 keyid equals to SHA1[12-19] over the total key content.
178 Steve Reid (SHA1)189 SHA1 algorithm contributors:
570 It's speed is comparable to SHA1 and there are no known attacks601 tristate "SHA1 digest algorithm"607 tristate "SHA1 digest algorithm (SSSE3/AVX/AVX2/SHA-NI)"641 tristate "SHA1 digest algorithm (OCTEON)"650 tristate "SHA1 digest algorithm (SPARC64)"659 tristate "SHA1 digest algorithm (powerpc)"666 tristate "SHA1 digest algorithm (PPC SPE)"673 tristate "SHA1 digest algorithm (x86_64 Multi-Buffer, Experimental)"
86 bool "SHA1 (default)"
58 ## code to compute oct SHA1 using SSE-256
1864 Default: Dependent on configuration. MD5 if available, else SHA1 if