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Searched refs:SET_VAL (Results 1 – 7 of 7) sorted by relevance

/linux-4.4.14/drivers/net/ethernet/apm/xgene/
Dxgene_enet_ring2.c30 ring_cfg[0] |= SET_VAL(X2_INTLINE, ring->id & RING_BUFNUM_MASK); in xgene_enet_ring_init()
33 ring_cfg[0] |= SET_VAL(X2_CFGCRID, 1); in xgene_enet_ring_init()
36 ring_cfg[2] |= QCOHERENT | SET_VAL(RINGADDRL, addr); in xgene_enet_ring_init()
39 ring_cfg[3] |= SET_VAL(RINGSIZE, ring->cfgsize) in xgene_enet_ring_init()
41 | SET_VAL(RINGADDRH, addr); in xgene_enet_ring_init()
42 ring_cfg[4] |= SET_VAL(X2_SELTHRSH, 1); in xgene_enet_ring_init()
54 ring_cfg[4] |= SET_VAL(X2_RINGTYPE, val); in xgene_enet_ring_set_type()
56 ring_cfg[3] |= SET_VAL(RINGMODE, BUFPOOL_MODE); in xgene_enet_ring_set_type()
64 ring_cfg[4] |= SET_VAL(X2_RECOMTIMEOUT, 0x7); in xgene_enet_ring_set_recombbuf()
174 data = SET_VAL(X2_INTLINE, ring->id & RING_BUFNUM_MASK) | in xgene_enet_wr_cmd()
Dxgene_enet_main.c44 SET_VAL(FPQNUM, buf_pool->dst_ring_num) | in xgene_enet_init_bufpool()
45 SET_VAL(STASH, 3)); in xgene_enet_init_bufpool()
84 raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) | in xgene_enet_refill_bufpool()
85 SET_VAL(BUFDATALEN, bufdatalen) | in xgene_enet_refill_bufpool()
250 hopinfo |= SET_VAL(TCPHDR, l4hlen) | in xgene_enet_work_msg()
251 SET_VAL(IPHDR, l3hlen) | in xgene_enet_work_msg()
252 SET_VAL(ETHHDR, ethhdr) | in xgene_enet_work_msg()
253 SET_VAL(EC, csum_enable) | in xgene_enet_work_msg()
254 SET_VAL(IS, proto) | in xgene_enet_work_msg()
268 desc[idx ^ 1] = cpu_to_le64(SET_VAL(DATAADDR, addr) | in xgene_set_addr_len()
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Dxgene_enet_main.h206 #define SET_VAL(field, val) \ macro
/linux-4.4.14/drivers/net/wireless/ath/carl9170/
Dphy.c461 SET_VAL(AR9170_PHY_SETTLING_SWITCH, val, m->switchSettling); in carl9170_init_phy_from_eeprom()
467 SET_VAL(AR9170_PHY_DESIRED_SZ_PGA, val, m->pgaDesiredSize); in carl9170_init_phy_from_eeprom()
468 SET_VAL(AR9170_PHY_DESIRED_SZ_ADC, val, m->adcDesiredSize); in carl9170_init_phy_from_eeprom()
473 SET_VAL(AR9170_PHY_RF_CTL4_TX_END_XPAB_OFF, val, m->txEndToXpaOff); in carl9170_init_phy_from_eeprom()
474 SET_VAL(AR9170_PHY_RF_CTL4_TX_END_XPAA_OFF, val, m->txEndToXpaOff); in carl9170_init_phy_from_eeprom()
475 SET_VAL(AR9170_PHY_RF_CTL4_FRAME_XPAB_ON, val, m->txFrameToXpaOn); in carl9170_init_phy_from_eeprom()
476 SET_VAL(AR9170_PHY_RF_CTL4_FRAME_XPAA_ON, val, m->txFrameToXpaOn); in carl9170_init_phy_from_eeprom()
481 SET_VAL(AR9170_PHY_RF_CTL3_TX_END_TO_A2_RX_ON, val, m->txEndToRxOn); in carl9170_init_phy_from_eeprom()
491 SET_VAL(AR9170_PHY_RXGAIN_TXRX_ATTEN, val, m->txRxAttenCh[0]); in carl9170_init_phy_from_eeprom()
497 SET_VAL(AR9170_PHY_RXGAIN_TXRX_ATTEN, val, m->txRxAttenCh[1]); in carl9170_init_phy_from_eeprom()
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Dmac.c420 SET_VAL(AR9170_MAC_BCN_DTIM, v, in carl9170_set_beacon_timers()
438 SET_VAL(AR9170_MAC_BCN_DTIM, v, in carl9170_set_beacon_timers()
463 SET_VAL(AR9170_MAC_BCN_PERIOD, v, ar->global_beacon_int); in carl9170_set_beacon_timers()
464 SET_VAL(AR9170_MAC_PRETBTT, pretbtt, ar->global_pretbtt); in carl9170_set_beacon_timers()
465 SET_VAL(AR9170_MAC_PRETBTT2, pretbtt, ar->global_pretbtt); in carl9170_set_beacon_timers()
Dtx.c785 SET_VAL(AR9170_TX_PHY_MCS, phyrate, txrate->idx); in carl9170_tx_physet()
940 SET_VAL(CARL9170_TX_SUPER_RI_TRIES, txc->s.ri[i], in carl9170_tx_apply_rateset()
997 SET_VAL(CARL9170_TX_SUPER_MISC_QUEUE, txc->s.misc, hw_queue); in carl9170_tx_prepare()
1000 SET_VAL(CARL9170_TX_SUPER_MISC_VIF_ID, txc->s.misc, cvif->id); in carl9170_tx_prepare()
1057 SET_VAL(CARL9170_TX_SUPER_AMPDU_DENSITY, in carl9170_tx_prepare()
1060 SET_VAL(CARL9170_TX_SUPER_AMPDU_FACTOR, in carl9170_tx_prepare()
1278 SET_VAL(CARL9170_TX_SUPER_MISC_QUEUE, q, in carl9170_tx_drop()
1580 SET_VAL(AR9170_MAC_BCN_HT1_PWR_CTRL, *ht1, 7); in carl9170_tx_beacon_physet()
1581 SET_VAL(AR9170_MAC_BCN_HT1_TPC, *ht1, power); in carl9170_tx_beacon_physet()
1582 SET_VAL(AR9170_MAC_BCN_HT1_CHAIN_MASK, *ht1, chains); in carl9170_tx_beacon_physet()
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Dhw.h805 #define SET_VAL(reg, value, newvalue) \ macro