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/linux-4.4.14/Documentation/devicetree/bindings/memory-controllers/
Dmvebu-sdram-controller.txt1 Device Tree bindings for MVEBU SDRAM controllers
3 The Marvell EBU SoCs all have a SDRAM controller. The SDRAM controller
8 Armada XP SDRAM controller.
14 include all SDRAM controller registers as per the datasheet.
Drenesas-memory-controllers.txt7 (DBSC3)", "SDRAM Bus State Controller (SBSC)").
Dti-aemif.txt7 per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM
/linux-4.4.14/arch/arm/mach-s3c24xx/
Dsleep-s3c2410.S53 orr r7, r7, #S3C2410_REFRESH_SELF @ SDRAM sleep command
54 orr r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals
65 streq r7, [r4] @ SDRAM sleep command
66 streq r8, [r5] @ SDRAM power-down config
/linux-4.4.14/Documentation/devicetree/bindings/arm/altera/
Dsocfpga-sdram-edac.txt1 Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
2 The EDAC accesses a range of registers in the SDRAM controller.
7 - interrupts : Should contain the SDRAM ECC IRQ in the
Dsocfpga-sdram-controller.txt1 Altera SOCFPGA SDRAM Controller
5 syscon is required by the Altera SOCFPGA SDRAM EDAC.
/linux-4.4.14/arch/arm/mach-pxa/
Dsleep.S54 @ prepare SDRAM refresh settings
58 @ enable SDRAM self-refresh mode
95 @ prepare SDRAM refresh settings
99 @ enable SDRAM self-refresh mode
106 @ We keep the change-down close to the actual suspend on SDRAM
159 @ external accesses after SDRAM is put in self-refresh mode
165 @ put SDRAM into self-refresh
/linux-4.4.14/drivers/staging/media/davinci_vpfe/
Ddavinci-vpfe-mc.txt102 1: tvp514x/tvp7002/mt9p031---> DAVINCI ISIF---> SDRAM
109 DAVINCI CROP RESIZER--->DAVINCI RESIZER [A/B]---> SDRAM
116 DAVINCI IPIPE---> DAVINCI CROP RESIZER--->DAVINCI RESIZER [A/B]---> SDRAM
121 1: SDRAM---> DAVINCI IPIPEIF---> DAVINCI IPIPE---> DAVINCI CROP RESIZER--->|
126 DAVINCI RESIZER [A/B]---> SDRAM
128 2: SDRAM---> DAVINCI IPIPEIF---> DAVINCI CROP RESIZER--->|
133 DAVINCI RESIZER [A/B]---> SDRAM
/linux-4.4.14/arch/frv/kernel/
Dhead-mmu-fr451.S40 # describe the position and layout of the SDRAM controller registers
44 # GR11 - displacement of 2nd SDRAM addr reg from GR14
45 # GR12 - displacement of 3rd SDRAM addr reg from GR14
46 # GR13 - displacement of 4th SDRAM addr reg from GR14
47 # GR14 - address of 1st SDRAM addr reg
48 # GR15 - amount to shift address by to match SDRAM addr reg
168 # determine the total SDRAM size
171 # GR25 - SDRAM size
183 sethi.p %hi(0xfe000000),gr17 ; unused SDRAM DBR value
225 # GR25 SDRAM size [saved]
Dhead-uc-fr401.S39 # describe the position and layout of the SDRAM controller registers
43 # GR11 - displacement of 2nd SDRAM addr reg from GR14
44 # GR12 - displacement of 3rd SDRAM addr reg from GR14
45 # GR13 - displacement of 4th SDRAM addr reg from GR14
46 # GR14 - address of 1st SDRAM addr reg
47 # GR15 - amount to shift address by to match SDRAM addr reg
173 # determine the total SDRAM size
176 # GR25 - SDRAM size
188 sethi.p %hi(0xfe000000),gr17 ; unused SDRAM DBR value
236 # GR25 SDRAM size [saved]
Dhead-uc-fr555.S38 # describe the position and layout of the SDRAM controller registers
42 # GR11 - displacement of 2nd SDRAM addr reg from GR14
43 # GR12 - displacement of 3rd SDRAM addr reg from GR14
44 # GR13 - displacement of 4th SDRAM addr reg from GR14
45 # GR14 - address of 1st SDRAM addr reg
46 # GR15 - amount to shift address by to match SDRAM addr reg
161 # determine the total SDRAM size
164 # GR25 - SDRAM size
176 sethi.p %hi(0xfff),gr17 ; unused SDRAM AMK value
220 # GR25 SDRAM size saved
Dcmode.S84 # to access SDRAM and the internal resources.
114 # (6) Execute loading the dummy for SDRAM.
117 # (7) Set '1' to the DRCN.SR bit, and change SDRAM to the
154 # (14) Release the self-refresh of SDRAM.
Dhead.inc47 __sdram_base = 0x00000000 /* base address to which SDRAM relocated */
49 __sdram_base = __page_offset /* base address to which SDRAM relocated */
Dsleep.S135 # put SDRAM in self-refresh mode
143 # Execute dummy load from SDRAM
146 # put the SDRAM into self-refresh mode
152 # wait for SDRAM to reach self-refresh mode
189 # wake SDRAM from self-refresh mode
200 # wait for the SDRAM to stabilise
Dhead.S106 # we need to relocate the SDRAM to 0x00000000 (linux) or 0xC0000000 (uClinux)
423 # save the SDRAM details
559 # GR25 SDRAM size [saved]
Dhead-uc-fr451.S42 # GR25 SDRAM size [saved]
/linux-4.4.14/Documentation/video4linux/cx2341x/
Dfw-upload.txt35 - Write 0x0000001A to register 0x07FC to init the Encoder SDRAM's pre-charge.
36 - Write 0x80000640 to register 0x07F8 to init the Encoder SDRAM's refresh to 1us.
37 - Write 0x0000001A to register 0x08FC to init the Decoder SDRAM's pre-charge.
38 - Write 0x80000640 to register 0x08F8 to init the Decoder SDRAM's refresh to 1us.
Dfw-memory.txt85 0x07F8: Encoder SDRAM refresh
86 0x07FC: Encoder SDRAM pre-charge
93 0x08F8: Decoder SDRAM refresh
94 0x08FC: Decoder SDRAM pre-charge
/linux-4.4.14/Documentation/memory-devices/
Dti-emif.txt1 TI EMIF SDRAM Controller Driver:
25 SoCs. EMIF is an SDRAM controller that, based on its revision,
26 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
/linux-4.4.14/drivers/memory/
DKconfig19 bool "Atmel (Multi-port DDR-)SDRAM Controller"
23 This driver is for Atmel SDRAM Controller or Atmel Multi-port
24 DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs.
45 SoCs. EMIF is an SDRAM controller that, based on its revision,
46 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
/linux-4.4.14/Documentation/devicetree/bindings/memory-controllers/ti/
Demif.txt1 * EMIF family of TI SDRAM controllers
3 EMIF - External Memory Interface - is an SDRAM controller used in
43 has capability for generating SDRAM temperature alerts
/linux-4.4.14/Documentation/devicetree/bindings/arm/omap/
Ddmm.txt4 SDRAM controllers (called EMIFs on OMAP). DMM manages various aspects of memory
5 accesses such as priority generation amongst initiators, configuration of SDRAM
/linux-4.4.14/arch/m32r/platforms/mappi2/
Ddot.gdbinit.vdec29 # Initialize SDRAM controller for Mappi
29 Mappi SDRAM controller initialization
33 # Initialize SDRAM controller for Mappi
54 Mappi SDRAM controller initialization
/linux-4.4.14/Documentation/frv/
Dfeatures.txt75 0xC0000000 - 0xCFFFFFFF SDRAM
90 The kernel reads the size of the SDRAM from the memory bus controller
93 The kernel initialisation code (1) adjusts the SDRAM base addresses to
94 move the SDRAM to desired address, (2) moves the kernel image down to the
95 bottom of SDRAM, (3) adjusts the bus controller registers to move I/O
118 tiled over the top of the SDRAM such that:
122 making sure no SDRAM is actually made unavailable by this approach.
125 of the SDRAM.
Dmmu-layout.txt46 00000000 - BFFFFFFF SDRAM SDRAM area
126 up to 3GB of SDRAM (possibly 3.25GB) to be made available. By using CONFIG_HIGHMEM, the kernel can
130 External devices can, of course, still DMA to and from all of the SDRAM, even if the kernel can't
Dbooting.txt174 Normally the kernel will work out how much SDRAM it has by reading the
175 SDRAM controller registers. That can be overridden with this
Dclock.txt44 Clock-SDRAM: 100.00 MHz
/linux-4.4.14/arch/powerpc/boot/dts/
Dsbc8548.dts28 0x3 0x0 0xf0000000 0x04000000 /*64MB SDRAM*/
29 0x4 0x0 0xf4000000 0x04000000 /*64MB SDRAM*/
Dsbc8548-altflash.dts31 0x3 0x0 0xf0000000 0x04000000 /*64MB SDRAM*/
32 0x4 0x0 0xf4000000 0x04000000 /*64MB SDRAM*/
Dsbc8349.dts275 0x2 0x0 0x10000000 0x04000000 /* 64MB SDRAM */
276 0x3 0x0 0x10000000 0x04000000>; /* 64MB SDRAM */
Dsbc8641d.dts79 3 0 0xe0000000 0x04000000 // 64MB LB SDRAM (CS3)
80 4 0 0xe4000000 0x04000000 // 64MB LB SDRAM (CS4)
/linux-4.4.14/drivers/video/fbdev/omap/
DKconfig52 bool "Set DMA SDRAM access priority high"
56 (SDRAM) this will speed up graphics DMA operations.
/linux-4.4.14/arch/arm/mach-omap2/
DKconfig134 bool "OMAP2 SDRAM Controller support"
233 access SDRAM during CORE DVFS, select Y here. This should boost
234 SDRAM performance at lower CORE OPPs. There are relatively few
/linux-4.4.14/arch/cris/arch-v10/lib/
Dhw_settings.S33 ; SDRAM or EDO DRAM?
Ddram_init.S39 ; Refer to ETRAX 100LX Designers Reference for a description of SDRAM initialization
/linux-4.4.14/arch/frv/
DKconfig91 The arch is, however, capable of supporting up to 3GB of SDRAM.
110 will rearrange the SDRAM layout to start at this address, and move
112 sufficiently less than 0xE0000000 that the SDRAM does not intersect
115 The base address must also be aligned such that the SDRAM controller
116 can decode it. For instance, a 512MB SDRAM bank must be 512MB aligned.
/linux-4.4.14/arch/cris/arch-v32/mach-fs/
DKconfig51 SDRAM configuration for group 0. The value depends on the
62 SDRAM configuration for group 1. The default value is 0
71 SDRAM timing parameters. The default value is ok for
81 SDRAM command. Should be 0 unless you really know what
Ddram_init.S25 ; Refer to BIF MDS for a description of SDRAM initialization
/linux-4.4.14/Documentation/arm/stm32/
Dstm32f429-overview.txt10 - External memory support through FMC controller (PSRAM, SDRAM, NOR, NAND)
/linux-4.4.14/arch/arm/mach-lpc32xx/
Dsuspend.S53 @ Wait for SDRAM busy status to go busy and then idle
/linux-4.4.14/arch/arm/mach-omap1/
Dsleep.S81 @ prepare to put SDRAM into self-refresh manually
166 @ prepare to put SDRAM into self-refresh manually
236 @ Prepare to put SDRAM into self-refresh manually
/linux-4.4.14/Documentation/arm/SA1100/
DPangolin3 It has EISA slots for ease of configuration with SDRAM/Flash
/linux-4.4.14/arch/cris/arch-v32/
DKconfig66 SDRAM configuration for group 0. The value depends on the
77 SDRAM configuration for group 1. The default value is 0
86 SDRAM timing parameters. The default value is ok for
96 SDRAM command. Should be 0 unless you really know what
/linux-4.4.14/Documentation/devicetree/bindings/clock/
Dmvebu-core-clock.txt30 3 = hclk (SDRAM Controller Internal Clock)
31 4 = dclk (SDRAM Interface Clock)
Dmvebu-gated-clock.txt151 6 dunit SDRAM Cntrl
/linux-4.4.14/arch/m32r/platforms/m32700ut/
Ddot.gdbinit_400MHz_32MB33 # Initialize SDRAM controller
53 SDRAM controller initialization
164 # SDRAM: 32MB
Ddot.gdbinit_200MHz_16MB33 # Initialize SDRAM controller
53 SDRAM controller initialization
164 # SDRAM: 16MB
Ddot.gdbinit_300MHz_32MB33 # Initialize SDRAM controller
53 SDRAM controller initialization
164 # SDRAM: 32MB
/linux-4.4.14/arch/cris/arch-v32/mach-a3/
DKconfig23 hex "DDR2 SDRAM timing"
26 SDRAM timing parameters.
/linux-4.4.14/arch/arm/mach-clps711x/
DKconfig16 headers. It comes with 16 MB SDRAM and 8 MB flash ROM.
/linux-4.4.14/arch/m32r/platforms/oaks32r/
Ddot.gdbinit.nommu30 # Initialize SDRAM controller
44 SDRAM controller initialization
/linux-4.4.14/arch/blackfin/
DKconfig446 bootloader settings. If the clocks are not set, the SDRAM settings
505 This sets the frequency of the system clock (including SDRAM or DDR) on
543 prompt "DDR SDRAM Chip Type"
556 prompt "DDR/SDRAM Timing"
560 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
561 The calculated SDRAM timing parameters may not be 100%
1063 Cached data will be written back to SDRAM only when needed.
1069 Cached data will always be written back to SDRAM when the
1080 Cached data will be written back to SDRAM only when needed.
1086 Cached data will always be written back to SDRAM when the
[all …]
/linux-4.4.14/arch/cris/arch-v10/
DKconfig279 bool "SDRAM support"
282 Enable this if you use SDRAM chips and configure
309 The R_SDRAM_CONFIG register specifies everything on how the SDRAM
320 Different SDRAM chips have different timing.
/linux-4.4.14/drivers/video/fbdev/aty/
Dmach64_ct.c352 else if (par->ram_type >= SDRAM) in aty_set_pll_ct()
467 case SDRAM: in aty_init_pll_ct()
555 if (M64_HAS(SDRAM_MAGIC_PLL) && (par->ram_type >= SDRAM)) in aty_init_pll_ct()
Datyfb_base.c2430 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM) in aty_init()
3055 if ((aty_ld_le32(CNFG_STAT0, par) & 7) >= SDRAM) in atyfb_setup_sparc()
/linux-4.4.14/arch/m32r/platforms/mappi/
Ddot.gdbinit48 # Initialize SDRAM controller
68 SDRAM controller initialization
Ddot.gdbinit.nommu48 # Initialize SDRAM controller
68 SDRAM controller initialization
Ddot.gdbinit.smp111 # Initialize SDRAM controller for Mappi
131 Mappi SDRAM controller initialization
/linux-4.4.14/arch/arm/boot/dts/
Dvexpress-v2p-ca9.dts248 /* DDR2 SDRAM and Test Chip DDR2 I/O supply */
257 /* DDR2 SDRAM VTT termination voltage */
/linux-4.4.14/arch/avr32/
DKconfig131 mapped into the 32-bit AVR memory bus. The FPGA offers two DDR2 SDRAM interfaces, which
150 well as a large SDRAM & Flash memory bank.
/linux-4.4.14/Documentation/devicetree/bindings/lpddr2/
Dlpddr2.txt1 * LPDDR2 SDRAM memories compliant to JEDEC JESD209-2
/linux-4.4.14/Documentation/arm/Samsung-S3C24XX/
DCPUfreq.txt66 SDRAM refresh rate.
DSuspend.txt8 The S3C24XX supports a low-power suspend mode, where the SDRAM is kept
/linux-4.4.14/Documentation/fb/
Dmatroxfb.txt159 G400: 0 -> 2x512Kx16 SDRAM, 16/32MB
163 3 -> 4x512Kx32 SDRAM, 32MB
165 5 -> 2x1Mx32 SDRAM, 32MB
178 sdram - tells to driver that you have Gxx0 with SDRAM memory.
294 + Gxx0 SGRAM/SDRAM is not autodetected.
Dep93xx-fb.txt134 In some cases it may be possible to reconfigure your SDRAM layout to
/linux-4.4.14/drivers/edac/
DKconfig371 bool "Altera SDRAM Memory Controller EDAC"
375 Altera SDRAM memory controller. Note that the
376 preloader must initialize the SDRAM before loading
/linux-4.4.14/Documentation/misc-devices/
Deeprom49 of an EEPROM (on a SDRAM DIMM for example). However, it will access serial
/linux-4.4.14/Documentation/devicetree/bindings/arm/
Datmel-at91.txt105 RAMC SDRAM/DDR Controller required properties:
/linux-4.4.14/Documentation/blockdev/
DREADME.DAC960104 32MB/64MB ECC SDRAM Memory
110 32MB/64MB ECC SDRAM Memory
116 32MB/64MB ECC SDRAM Memory
121 16MB/32MB/64MB ECC SDRAM Memory
126 Built in 16M ECC SDRAM Memory
133 16MB/32MB/64MB Parity SDRAM Memory with Battery Backup
/linux-4.4.14/arch/m32r/platforms/mappi3/
Ddot.gdbinit9 # Initialize SDRAM controller for Mappi
/linux-4.4.14/lib/
DKconfig475 Data from JEDEC specs for DDR SDRAM memories,
478 DDR SDRAM controllers.
/linux-4.4.14/arch/m32r/platforms/opsput/
Ddot.gdbinit202 # SDRAM
/linux-4.4.14/Documentation/cris/
DREADME38 * SDRAM
/linux-4.4.14/include/video/
Dmach64.h885 #define SDRAM 4 macro
/linux-4.4.14/Documentation/devicetree/bindings/bus/
Dmvebu-mbus.txt53 the second one controls the SDRAM decoding window and
/linux-4.4.14/arch/arm/mach-ixp4xx/
DKconfig168 32mb SDRAM
/linux-4.4.14/Documentation/arm/OMAP/
DDSS128 - Framebuffer is a memory area inside OMAP's SRAM/SDRAM that contains the
/linux-4.4.14/Documentation/scsi/
Darcmsr_spec.txt73 ** SDRAM Size 0x00000100(4)-->256 MB