Searched refs:SCLK_PWRMGT_CNTL (Results 1 - 21 of 21) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/radeon/
H A Drv770_dpm.c134 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); rv770_gfx_clock_gating_enable()
136 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); rv770_gfx_clock_gating_enable()
137 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); rv770_gfx_clock_gating_enable()
138 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); rv770_gfx_clock_gating_enable()
173 if (RREG32(SCLK_PWRMGT_CNTL) & DYN_GFX_CLK_OFF_EN) rv770_restore_cgcg()
177 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); rv770_restore_cgcg()
182 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); rv770_start_dpm()
200 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); rv770_stop_dpm()
854 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); rv770_program_tp()
856 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); rv770_program_tp()
858 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); rv770_program_tp()
860 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); rv770_program_tp()
1633 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
1634 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
1635 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
1664 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
H A Dcypress_dpm.c103 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
104 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
105 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
141 WREG32_P(SCLK_PWRMGT_CNTL, DYN_LIGHT_SLEEP_EN, ~DYN_LIGHT_SLEEP_EN); cypress_gfx_clock_gating_enable()
143 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); cypress_gfx_clock_gating_enable()
145 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); cypress_gfx_clock_gating_enable()
146 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); cypress_gfx_clock_gating_enable()
147 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); cypress_gfx_clock_gating_enable()
151 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_LIGHT_SLEEP_EN); cypress_gfx_clock_gating_enable()
248 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); cypress_enable_sclk_control()
250 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); cypress_enable_sclk_control()
H A Dr600_dpm.c244 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); r600_gfx_clockgating_enable()
246 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); r600_gfx_clockgating_enable()
303 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); r600_enable_sclk_control()
305 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); r600_enable_sclk_control()
358 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); r600_select_td()
360 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); r600_select_td()
362 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); r600_select_td()
364 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); r600_select_td()
H A Dsumo_dpm.c92 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); sumo_gfx_clockgating_enable()
94 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); sumo_gfx_clockgating_enable()
95 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); sumo_gfx_clockgating_enable()
96 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); sumo_gfx_clockgating_enable()
442 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); sumo_program_tp()
444 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); sumo_program_tp()
447 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); sumo_program_tp()
450 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); sumo_program_tp()
918 WREG32_P(SCLK_PWRMGT_CNTL, FIR_RESET, ~FIR_RESET); sumo_reset_am()
923 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_RESET); sumo_start_am()
H A Dtrinity_dpm.c445 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); trinity_gfx_clockgating_enable()
447 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); trinity_gfx_clockgating_enable()
448 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); trinity_gfx_clockgating_enable()
449 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); trinity_gfx_clockgating_enable()
508 WREG32_P(SCLK_PWRMGT_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN); trinity_gfx_powergating_enable()
510 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_PWR_DOWN_EN); trinity_gfx_powergating_enable()
772 if (RREG32(SCLK_PWRMGT_CNTL) & DYNAMIC_PM_EN) trinity_wait_for_dpm_enabled()
803 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~(RESET_SCLK_CNT | RESET_BUSY_CNT)); trinity_start_am()
808 WREG32_P(SCLK_PWRMGT_CNTL, RESET_SCLK_CNT | RESET_BUSY_CNT, trinity_reset_am()
H A Drv730d.h83 #define SCLK_PWRMGT_CNTL 0x644 macro
H A Dtrinityd.h175 #define SCLK_PWRMGT_CNTL 0x678 macro
H A Drv730_dpm.c453 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); rv730_start_dpm()
471 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); rv730_stop_dpm()
H A Dsumod.h152 #define SCLK_PWRMGT_CNTL 0x644 macro
H A Dci_dpm.c1528 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); ci_start_dpm()
1530 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); ci_start_dpm()
1589 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); ci_stop_dpm()
1591 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); ci_stop_dpm()
1612 u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); ci_enable_sclk_control()
1618 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); ci_enable_sclk_control()
2031 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); ci_program_vc()
2033 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); ci_program_vc()
2049 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); ci_clear_vc()
2051 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); ci_clear_vc()
H A Dkv_dpm.c660 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); kv_start_am()
665 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl); kv_start_am()
670 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); kv_reset_am()
674 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl); kv_reset_am()
H A Drv770d.h158 #define SCLK_PWRMGT_CNTL 0x644 macro
H A Dsi_dpm.c3358 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); si_enable_sclk_control()
3360 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); si_enable_sclk_control()
3790 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); si_program_tp()
3792 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); si_program_tp()
3795 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); si_program_tp()
3798 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); si_program_tp()
H A Dnid.h599 #define SCLK_PWRMGT_CNTL 0x644 macro
H A Dsid.h251 #define SCLK_PWRMGT_CNTL 0x788 macro
H A Dcikd.h111 #define SCLK_PWRMGT_CNTL 0xC0200008 macro
H A Dni_dpm.c1205 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
1206 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
1207 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
H A Devergreend.h137 #define SCLK_PWRMGT_CNTL 0x644 macro
H A Dr600d.h1307 #define SCLK_PWRMGT_CNTL 0x620 macro
/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
H A Dkv_dpm.c3191 dev_info(adev->dev, " SCLK_PWRMGT_CNTL=0x%08X\n", kv_dpm_print_status()
H A Dci_dpm.c6389 dev_info(adev->dev, " SCLK_PWRMGT_CNTL=0x%08X\n", ci_dpm_print_status()

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