Searched refs:SCLK_MUX_SEL_MASK (Results 1 - 15 of 15) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/radeon/
H A Drv740d.h36 #define SCLK_MUX_SEL_MASK (0x1ff << 0) macro
H A Drv730d.h39 #define SCLK_MUX_SEL_MASK (0x1ff << 0) macro
H A Drv740_dpm.c152 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; rv740_populate_sclk_value()
371 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; rv740_populate_smc_acpi_state()
H A Drv730_dpm.c84 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; rv730_populate_sclk_value()
294 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; rv730_populate_smc_acpi_state()
H A Drv770d.h102 #define SCLK_MUX_SEL_MASK (0x1ff << 0) macro
H A Drv770_dpm.c531 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; rv770_populate_sclk_value()
979 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; rv770_populate_smc_acpi_state()
H A Dnid.h549 #define SCLK_MUX_SEL_MASK (0x1ff << 0) macro
H A Drv770.c1140 tmp &= SCLK_MUX_SEL_MASK; rv770_set_clk_bypass_mode()
H A Dsid.h96 #define SCLK_MUX_SEL_MASK (0x1ff << 0) macro
H A Dcikd.h261 #define SCLK_MUX_SEL_MASK (0x1ff << 0) macro
H A Dcypress_dpm.c1430 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; cypress_populate_smc_acpi_state()
H A Devergreend.h84 #define SCLK_MUX_SEL_MASK (0x1ff << 0) macro
H A Dni_dpm.c1902 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; ni_populate_smc_acpi_state()
2033 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; ni_calculate_sclk_params()
H A Dsi_dpm.c4588 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; si_populate_smc_acpi_state()
4828 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; si_calculate_sclk_params()
H A Dci_dpm.c2995 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; ci_populate_smc_acpi_level()

Completed in 418 milliseconds