Searched refs:RegAddr (Results 1 - 14 of 14) sorted by relevance

/linux-4.4.14/drivers/staging/rtl8723au/hal/
H A Dodm_interface.c29 u32 RegAddr, ODM_SetRFReg()
36 PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data); ODM_SetRFReg()
42 u32 RegAddr, ODM_GetRFReg()
48 return PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask); ODM_GetRFReg()
26 ODM_SetRFReg( struct dm_odm_t *pDM_Odm, enum RF_RADIO_PATH eRFPath, u32 RegAddr, u32 BitMask, u32 Data ) ODM_SetRFReg() argument
39 ODM_GetRFReg( struct dm_odm_t *pDM_Odm, enum RF_RADIO_PATH eRFPath, u32 RegAddr, u32 BitMask ) ODM_GetRFReg() argument
H A Drtl8723a_phycfg.c76 * u32 RegAddr, Target address to be readback
87 PHY_QueryBBReg(struct rtw_adapter *Adapter, u32 RegAddr, u32 BitMask) PHY_QueryBBReg() argument
91 OriginalValue = rtl8723au_read32(Adapter, RegAddr); PHY_QueryBBReg()
104 * u32 RegAddr, Target address to be modified
120 PHY_SetBBReg(struct rtw_adapter *Adapter, u32 RegAddr, u32 BitMask, u32 Data) PHY_SetBBReg() argument
125 OriginalValue = rtl8723au_read32(Adapter, RegAddr); PHY_SetBBReg()
130 rtl8723au_write32(Adapter, RegAddr, Data); PHY_SetBBReg()
132 /* RTPRINT(FPHY, PHY_BBW, ("BBW MASK = 0x%lx Addr[0x%lx]= 0x%lx\n", BitMask, RegAddr, Data)); */ PHY_SetBBReg()
329 * u32 RegAddr, The target address to be read
342 u32 RegAddr, u32 BitMask) PHY_QueryRFReg()
349 Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr); PHY_QueryRFReg()
365 * u32 RegAddr, The target address to be modified
379 u32 RegAddr, u32 BitMask, u32 Data) PHY_SetRFReg()
387 Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr); PHY_SetRFReg()
392 phy_RFSerialWrite(Adapter, eRFPath, RegAddr, Data); PHY_SetRFReg()
541 storePwrIndexDiffRateOffset(struct rtw_adapter *Adapter, u32 RegAddr, storePwrIndexDiffRateOffset() argument
546 if (RegAddr == rTxAGC_A_Rate18_06) { storePwrIndexDiffRateOffset()
549 if (RegAddr == rTxAGC_A_Rate54_24) { storePwrIndexDiffRateOffset()
552 if (RegAddr == rTxAGC_A_CCK1_Mcs32) { storePwrIndexDiffRateOffset()
555 if (RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0xffffff00) { storePwrIndexDiffRateOffset()
558 if (RegAddr == rTxAGC_A_Mcs03_Mcs00) { storePwrIndexDiffRateOffset()
561 if (RegAddr == rTxAGC_A_Mcs07_Mcs04) { storePwrIndexDiffRateOffset()
564 if (RegAddr == rTxAGC_A_Mcs11_Mcs08) { storePwrIndexDiffRateOffset()
567 if (RegAddr == rTxAGC_A_Mcs15_Mcs12) { storePwrIndexDiffRateOffset()
570 if (RegAddr == rTxAGC_B_Rate18_06) { storePwrIndexDiffRateOffset()
573 if (RegAddr == rTxAGC_B_Rate54_24) { storePwrIndexDiffRateOffset()
576 if (RegAddr == rTxAGC_B_CCK1_55_Mcs32) { storePwrIndexDiffRateOffset()
579 if (RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0x000000ff) { storePwrIndexDiffRateOffset()
582 if (RegAddr == rTxAGC_B_Mcs03_Mcs00) { storePwrIndexDiffRateOffset()
585 if (RegAddr == rTxAGC_B_Mcs07_Mcs04) { storePwrIndexDiffRateOffset()
588 if (RegAddr == rTxAGC_B_Mcs11_Mcs08) { storePwrIndexDiffRateOffset()
591 if (RegAddr == rTxAGC_B_Mcs15_Mcs12) { storePwrIndexDiffRateOffset()
341 PHY_QueryRFReg(struct rtw_adapter *Adapter, enum RF_RADIO_PATH eRFPath, u32 RegAddr, u32 BitMask) PHY_QueryRFReg() argument
378 PHY_SetRFReg(struct rtw_adapter *Adapter, enum RF_RADIO_PATH eRFPath, u32 RegAddr, u32 BitMask, u32 Data) PHY_SetRFReg() argument
H A Dodm_RegConfig8723A.c25 u32 RegAddr odm_ConfigRFReg_8723A()
41 ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); odm_ConfigRFReg_8723A()
/linux-4.4.14/drivers/staging/rtl8723au/include/
H A Dodm_interface.h58 u32 RegAddr, u32 BitMask, u32 Data);
60 u32 RegAddr, u32 BitMask);
H A DHal8723APhyCfg.h110 u32 PHY_QueryBBReg(struct rtw_adapter *Adapter, u32 RegAddr,
112 void PHY_SetBBReg(struct rtw_adapter *Adapter, u32 RegAddr,
115 enum RF_RADIO_PATH eRFPath, u32 RegAddr,
118 enum RF_RADIO_PATH eRFPath, u32 RegAddr,
H A Dodm_RegConfig8723A.h19 enum RF_RADIO_PATH RF_PATH, u32 RegAddr);
/linux-4.4.14/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_phy.h71 u32 RegAddr, u32 BitMask, u32 Data);
73 u32 RegAddr, u32 BitMask);
H A Dr8192E_phy.c211 u32 RegAddr, u32 BitMask, u32 Data) rtl92e_set_rf_reg()
225 RegAddr); rtl92e_set_rf_reg()
230 _rtl92e_phy_rf_fw_write(dev, eRFPath, RegAddr, rtl92e_set_rf_reg()
233 _rtl92e_phy_rf_fw_write(dev, eRFPath, RegAddr, Data); rtl92e_set_rf_reg()
239 RegAddr); rtl92e_set_rf_reg()
244 _rtl92e_phy_rf_write(dev, eRFPath, RegAddr, New_Value); rtl92e_set_rf_reg()
246 _rtl92e_phy_rf_write(dev, eRFPath, RegAddr, Data); rtl92e_set_rf_reg()
251 u32 RegAddr, u32 BitMask) rtl92e_get_rf_reg()
262 Original_Value = _rtl92e_phy_rf_fw_read(dev, eRFPath, RegAddr); rtl92e_get_rf_reg()
265 Original_Value = _rtl92e_phy_rf_read(dev, eRFPath, RegAddr); rtl92e_get_rf_reg()
210 rtl92e_set_rf_reg(struct net_device *dev, enum rf90_radio_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data) rtl92e_set_rf_reg() argument
250 rtl92e_get_rf_reg(struct net_device *dev, enum rf90_radio_path eRFPath, u32 RegAddr, u32 BitMask) rtl92e_get_rf_reg() argument
/linux-4.4.14/drivers/staging/rtl8188eu/include/
H A Dhal_intf.h212 enum rf_radio_path eRFPath, u32 RegAddr,
289 u32 RegAddr, u32 BitMask);
/linux-4.4.14/drivers/tty/
H A Dsynclinkmp.c5538 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5540 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5543 RegAddr += 0x40; /* DMA access */ \
5545 RegAddr += 0x20; /* MSCI access */ \
5552 return *RegAddr; read_reg()
5557 *RegAddr = Value; write_reg()
5563 return *((u16 *)RegAddr); read_reg16()
5569 *((u16 *)RegAddr) = Value; write_reg16()
5574 unsigned char *RegAddr = (unsigned char *)info->statctrl_base; read_status_reg() local
5575 return *RegAddr; read_status_reg()
5580 unsigned char *RegAddr = (unsigned char *)info->statctrl_base; write_control_reg() local
5581 *RegAddr = info->port_array[0]->ctrlreg_value; write_control_reg()
H A Dsynclink.c4528 * RegAddr register address (number) for write
4536 static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue ) usc_OutDmaReg() argument
4541 outw( RegAddr + info->mbre_bit, info->io_base ); usc_OutDmaReg()
4558 * RegAddr register address (number) to read from
4565 static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr ) usc_InDmaReg()
4570 outw( RegAddr + info->mbre_bit, info->io_base ); usc_InDmaReg()
4584 * RegAddr register address (number) to write to
4592 static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue ) usc_OutReg() argument
4594 outw( RegAddr + info->loopback_bits, info->io_base + CCAR ); usc_OutReg()
4611 * RegAddr register address (number) to read from
4617 static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr ) usc_InReg()
4619 outw( RegAddr + info->loopback_bits, info->io_base + CCAR ); usc_InReg()
/linux-4.4.14/drivers/media/tuners/
H A Dmxl5005s.c3596 u8 RegAddr[] = { MXL_GetInitRegister() local
3601 *count = ARRAY_SIZE(RegAddr); MXL_GetInitRegister()
3606 RegNum[i] = RegAddr[i]; MXL_GetInitRegister()
3621 u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106, MXL_GetCHRegister() local
3624 u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106, MXL_GetCHRegister() local
3627 u8 RegAddr[171]; MXL_GetCHRegister()
3629 RegAddr[i] = i; MXL_GetCHRegister()
3633 *count = ARRAY_SIZE(RegAddr); MXL_GetCHRegister()
3636 RegNum[i] = RegAddr[i]; MXL_GetCHRegister()
3649 u8 RegAddr[] = {43, 136}; MXL_GetCHRegister_ZeroIF() local
3651 *count = ARRAY_SIZE(RegAddr); MXL_GetCHRegister_ZeroIF()
3654 RegNum[i] = RegAddr[i]; MXL_GetCHRegister_ZeroIF()
/linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dphy.c1879 "Invalid RegAddr 0x%x\n", regaddr); _rtl8821ae_get_rate_section_index()
/linux-4.4.14/drivers/net/ethernet/intel/e1000/
H A De1000_hw.c3051 * <Preamble><SOF><OpCode><PhyAddr><RegAddr><Turnaround><Data>. e1000_write_phy_reg_ex()

Completed in 499 milliseconds