Searched refs:RSI_CEATA_CONTROL (Results 1 – 5 of 5) sorted by relevance
51 #define bfin_read_RSI_CEATA_CTL() bfin_read16(RSI_CEATA_CONTROL)52 #define bfin_write_RSI_CEATA_CTL(val) bfin_write16(RSI_CEATA_CONTROL, val)
33 #define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */ macro
54 #define RSI_CEATA_CONTROL 0xFFC0064C /* RSI0 This register contains bit to dis CCS… macro
3223 #define bfin_read_RSI_CEATA_CONTROL() bfin_read16(RSI_CEATA_CONTROL)3224 #define bfin_write_RSI_CEATA_CONTROL(val) bfin_write16(RSI_CEATA_CONTROL, val)
1374 D16(RSI_CEATA_CONTROL); in bfin_debug_mmrs_init()