Searched refs:RREG32_PCIE (Results 1 – 10 of 10) sorted by relevance
1586 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); in cik_pcie_gen3_enable()1627 tmp = RREG32_PCIE(ixPCIE_LC_STATUS1); in cik_pcie_gen3_enable()1634 tmp = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL); in cik_pcie_gen3_enable()1659 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); in cik_pcie_gen3_enable()1663 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); in cik_pcie_gen3_enable()1691 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); in cik_pcie_gen3_enable()1714 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); in cik_pcie_gen3_enable()1719 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); in cik_pcie_gen3_enable()1739 orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); in cik_program_aspm()1746 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL3); in cik_program_aspm()[all …]
308 return RREG32_PCIE(index); in amdgpu_cgs_read_ind_register()
822 orig = data = RREG32_PCIE(ixPCIE_CNTL2); in gmc_v7_0_enable_bif_mgls()
4953 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL) & in ci_get_current_pcie_speed()4964 link_width = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL) & in ci_get_current_pcie_lane_number()6532 RREG32_PCIE(ixPCIE_LC_SPEED_CNTL)); in ci_dpm_print_status()6534 RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL)); in ci_dpm_print_status()
2148 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) macro
89 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_tlb_flush()91 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_tlb_flush()175 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_enable()195 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_disable()536 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()552 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()554 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()570 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_get_pcie_lanes()597 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_debugfs_pcie_gart_info()599 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); in rv370_debugfs_pcie_gart_info()[all …]
5559 orig = data = RREG32_PCIE(PCIE_CNTL2); in si_enable_bif_mgls()7479 tmp = RREG32_PCIE(PCIE_LC_STATUS1); in si_pcie_gen3_enable()7594 orig = data = RREG32_PCIE(PCIE_P_CNTL); in si_program_aspm()7757 orig = data = RREG32_PCIE(PCIE_CNTL2); in si_program_aspm()7765 data = RREG32_PCIE(PCIE_LC_STATUS1); in si_program_aspm()
131 tmp = RREG32_PCIE(PCIE_P_CNTL); in rv6xx_enable_pll_sleep_in_l1()
122 tmp = RREG32_PCIE(PCIE_P_CNTL); in rv770_enable_pll_sleep_in_l1()
2537 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) macro