Searched refs:REG_WR_INT (Results 1 - 72 of 72) sorted by relevance

/linux-4.4.14/arch/cris/arch-v32/mach-a3/
H A Darbiter.c274 REG_WR_INT(marb_bar, regi_marb_bar, rw_h264_rd_burst, 3); crisv32_arbiter_init()
275 REG_WR_INT(marb_bar, regi_marb_bar, rw_h264_wr_burst, 3); crisv32_arbiter_init()
276 REG_WR_INT(marb_bar, regi_marb_bar, rw_ccd_burst, 3); crisv32_arbiter_init()
277 REG_WR_INT(marb_bar, regi_marb_bar, rw_vin_wr_burst, 3); crisv32_arbiter_init()
278 REG_WR_INT(marb_bar, regi_marb_bar, rw_vin_rd_burst, 3); crisv32_arbiter_init()
279 REG_WR_INT(marb_bar, regi_marb_bar, rw_sclr_rd_burst, 3); crisv32_arbiter_init()
280 REG_WR_INT(marb_bar, regi_marb_bar, rw_vout_burst, 3); crisv32_arbiter_init()
281 REG_WR_INT(marb_bar, regi_marb_bar, rw_sclr_fifo_burst, 3); crisv32_arbiter_init()
282 REG_WR_INT(marb_bar, regi_marb_bar, rw_l2cache_burst, 3); crisv32_arbiter_init()
407 REG_WR_INT(marb_bar_bp, crisv32_arbiter_watch()
411 REG_WR_INT(marb_bar_bp, crisv32_arbiter_watch()
415 REG_WR_INT(marb_bar_bp, crisv32_arbiter_watch()
418 REG_WR_INT(marb_bar_bp, crisv32_arbiter_watch()
423 REG_WR_INT(marb_foo_bp, crisv32_arbiter_watch()
427 REG_WR_INT(marb_foo_bp, crisv32_arbiter_watch()
431 REG_WR_INT(marb_foo_bp, crisv32_arbiter_watch()
434 REG_WR_INT(marb_foo_bp, crisv32_arbiter_watch()
449 REG_WR_INT(marb_bar, regi_marb_bar, crisv32_arbiter_watch()
452 REG_WR_INT(marb_foo, regi_marb_foo, crisv32_arbiter_watch()
509 REG_WR_INT(marb_bar, regi_marb_bar, rw_intr_mask, crisv32_arbiter_unwatch()
512 REG_WR_INT(marb_foo, regi_marb_foo, rw_intr_mask, crisv32_arbiter_unwatch()
H A Dpinmux.c38 REG_WR_INT(pinmux, regi_pinmux, rw_hwprot, 0); crisv32_pinmux_init()
/linux-4.4.14/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/
H A Diop_version_defs.h45 #ifndef REG_WR_INT
46 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Diop_sap_in_defs.h45 #ifndef REG_WR_INT
46 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Diop_sap_out_defs.h45 #ifndef REG_WR_INT
46 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Diop_sw_spu_defs.h45 #ifndef REG_WR_INT
46 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Diop_sw_cfg_defs.h45 #ifndef REG_WR_INT
46 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Diop_sw_cpu_defs.h45 #ifndef REG_WR_INT
46 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Diop_sw_mpu_defs.h45 #ifndef REG_WR_INT
46 #define REG_WR_INT( scope, inst, reg, val ) \ macro
/linux-4.4.14/arch/cris/arch-v32/drivers/
H A Diop_fw_load.c111 REG_WR_INT(iop_spu, regi_iop_spu0, rw_seq_pc, (i*4)); iop_fw_load_spu()
114 REG_WR_INT(iop_spu, regi_iop_spu1, rw_seq_pc, (i*4)); iop_fw_load_spu()
117 REG_WR_INT(iop_sw_cpu, regi_iop_sw_cpu, rw_mc_data, *data); iop_fw_load_spu()
158 REG_WR_INT(iop_mpu, regi_iop_mpu, rw_immediate, *data); iop_fw_load_mpu()
183 REG_WR_INT(iop_mpu, regi_iop_mpu, rw_instr, MPU_BA_I(start_addr)); iop_start_mpu()
/linux-4.4.14/arch/cris/include/arch-v32/arch/hwregs/
H A Ddma.h108 do { REG_WR_INT( dma, inst, rw_group, (int) group_descr ); \
116 do { REG_WR_INT( dma, inst, rw_group_down, (int) ctx_descr ); \
H A Dirq_nmi_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Dstrcop_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Dconfig_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Drt_trace_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Data_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Dbif_slave_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Dmarb_bp_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Dmarb_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
307 #ifndef REG_WR_INT
308 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Dbif_core_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Deth_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Dextmem_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Dser_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Dsser_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Dbif_dma_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Ddma_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
/linux-4.4.14/arch/cris/include/arch-v32/arch/hwregs/iop/
H A Diop_version_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Diop_fifo_in_extra_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Diop_fifo_out_extra_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Diop_scrc_in_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Diop_scrc_out_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Diop_trigger_grp_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Diop_crc_par_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Diop_fifo_in_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Diop_mpu_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Diop_sap_in_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Diop_timer_grp_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Diop_dmc_in_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Diop_dmc_out_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Diop_fifo_out_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Diop_sap_out_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Diop_spu_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Diop_sw_spu_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Diop_sw_cfg_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Diop_sw_cpu_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Diop_sw_mpu_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
/linux-4.4.14/arch/cris/include/arch-v32/mach-a3/mach/hwregs/
H A Dstrmux_defs.h45 #ifndef REG_WR_INT
46 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Dclkgen_defs.h45 #ifndef REG_WR_INT
46 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Dl2cache_defs.h45 #ifndef REG_WR_INT
46 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Dmarb_bar_defs.h45 #ifndef REG_WR_INT
46 #define REG_WR_INT( scope, inst, reg, val ) \ macro
329 #ifndef REG_WR_INT
330 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Dmarb_foo_defs.h45 #ifndef REG_WR_INT
46 #define REG_WR_INT( scope, inst, reg, val ) \ macro
455 #ifndef REG_WR_INT
456 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Dddr2_defs.h45 #ifndef REG_WR_INT
46 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Dintr_vect_defs.h45 #ifndef REG_WR_INT
46 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Dpinmux_defs.h45 #ifndef REG_WR_INT
46 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Dpio_defs.h45 #ifndef REG_WR_INT
46 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Dtimer_defs.h45 #ifndef REG_WR_INT
46 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Dgio_defs.h45 #ifndef REG_WR_INT
46 #define REG_WR_INT( scope, inst, reg, val ) \ macro
/linux-4.4.14/arch/cris/arch-v32/kernel/
H A Ddebugport.c181 REG_WR_INT(ser, kgdb_port->instance, rw_dout, val); putDebugChar()
192 REG_WR_INT(ser, port->instance, rw_dout, c); early_putch()
/linux-4.4.14/arch/cris/include/arch-v32/mach-fs/mach/hwregs/
H A Dconfig_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Dstrmux_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Dbif_slave_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Dintr_vect_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Dmarb_bp_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Dmarb_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
307 #ifndef REG_WR_INT
308 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Dbif_core_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Dgio_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Dpinmux_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Dtimer_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
H A Dbif_dma_defs.h48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \ macro
/linux-4.4.14/arch/cris/arch-v32/mach-fs/
H A Darbiter.c289 REG_WR_INT(marb_bp, watches[i].instance, rw_first_addr, crisv32_arbiter_watch()
291 REG_WR_INT(marb_bp, watches[i].instance, rw_last_addr, crisv32_arbiter_watch()
293 REG_WR_INT(marb_bp, watches[i].instance, rw_op, crisv32_arbiter_watch()
295 REG_WR_INT(marb_bp, watches[i].instance, rw_clients, crisv32_arbiter_watch()
H A Dpinmux.c60 REG_WR_INT(pinmux, regi_pinmux, rw_hwprot, 0); crisv32_pinmux_init()
/linux-4.4.14/drivers/tty/serial/
H A Detraxfs-uart.c75 REG_WR_INT(ser, up->regi_ser, rw_dout, '\r'); cris_console_write()
81 REG_WR_INT(ser, up->regi_ser, rw_dout, s[i]); cris_console_write()
602 REG_WR_INT(ser, up->regi_ser, rw_dout, c); etraxfs_uart_put_poll_char()

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