Searched refs:REG_VAL (Results 1 - 4 of 4) sorted by relevance

/linux-4.4.14/drivers/clk/bcm/
H A Dclk-nsp.c24 #define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, } macro
50 .ndiv_int = REG_VAL(0x14, 20, 10),
51 .ndiv_frac = REG_VAL(0x14, 0, 20),
52 .pdiv = REG_VAL(0x18, 24, 3),
53 .status = REG_VAL(0x20, 12, 1),
61 .mdiv = REG_VAL(0x18, 16, 8),
67 .mdiv = REG_VAL(0x18, 8, 8),
73 .mdiv = REG_VAL(0x18, 0, 8),
79 .mdiv = REG_VAL(0x1c, 16, 8),
85 .mdiv = REG_VAL(0x1c, 8, 8),
91 .mdiv = REG_VAL(0x1c, 0, 8),
107 .ndiv_int = REG_VAL(0x4, 20, 8),
108 .ndiv_frac = REG_VAL(0x4, 0, 20),
109 .pdiv = REG_VAL(0x4, 28, 3),
110 .status = REG_VAL(0x10, 12, 1),
118 .mdiv = REG_VAL(0x8, 24, 8),
124 .mdiv = REG_VAL(0x8, 16, 8),
130 .mdiv = REG_VAL(0x8, 8, 8),
H A Dclk-ns2.c24 #define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, } macro
46 .ndiv_int = REG_VAL(0x8, 4, 10),
47 .pdiv = REG_VAL(0x8, 0, 4),
49 .status = REG_VAL(0x0, 27, 1),
62 .mdiv = REG_VAL(0x18, 0, 8),
68 .mdiv = REG_VAL(0x18, 8, 8),
74 .mdiv = REG_VAL(0x14, 0, 8),
80 .mdiv = REG_VAL(0x14, 8, 8),
86 .mdiv = REG_VAL(0x14, 16, 8),
92 .mdiv = REG_VAL(0x14, 24, 8),
109 .ndiv_int = REG_VAL(0x8, 4, 10),
110 .pdiv = REG_VAL(0x8, 0, 4),
112 .status = REG_VAL(0x0, 13, 1),
124 .mdiv = REG_VAL(0x18, 0, 8),
130 .mdiv = REG_VAL(0x18, 8, 8),
136 .mdiv = REG_VAL(0x14, 0, 8),
142 .mdiv = REG_VAL(0x14, 8, 8),
148 .mdiv = REG_VAL(0x14, 16, 8),
154 .mdiv = REG_VAL(0x14, 24, 8),
171 .ndiv_int = REG_VAL(0x8, 4, 10),
172 .pdiv = REG_VAL(0x8, 0, 4),
174 .status = REG_VAL(0x0, 0, 1),
186 .mdiv = REG_VAL(0x14, 0, 8),
192 .mdiv = REG_VAL(0x14, 8, 8),
198 .mdiv = REG_VAL(0x10, 0, 8),
204 .mdiv = REG_VAL(0x10, 8, 8),
210 .mdiv = REG_VAL(0x10, 16, 8),
216 .mdiv = REG_VAL(0x10, 24, 8),
233 .ndiv_int = REG_VAL(0x8, 4, 10),
234 .pdiv = REG_VAL(0x8, 0, 4),
236 .status = REG_VAL(0x0, 0, 1),
248 .mdiv = REG_VAL(0x14, 0, 8),
254 .mdiv = REG_VAL(0x14, 8, 8),
260 .mdiv = REG_VAL(0x10, 0, 8),
266 .mdiv = REG_VAL(0x10, 8, 8),
272 .mdiv = REG_VAL(0x10, 16, 8),
278 .mdiv = REG_VAL(0x10, 24, 8),
H A Dclk-cygnus.c26 #define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, } macro
64 .ndiv_int = REG_VAL(0x10, 20, 10),
65 .ndiv_frac = REG_VAL(0x10, 0, 20),
66 .pdiv = REG_VAL(0x14, 0, 4),
68 .status = REG_VAL(0x28, 12, 1),
76 .mdiv = REG_VAL(0x20, 0, 8),
82 .mdiv = REG_VAL(0x20, 10, 8),
88 .mdiv = REG_VAL(0x20, 20, 8),
94 .mdiv = REG_VAL(0x24, 0, 8),
100 .mdiv = REG_VAL(0x24, 10, 8),
106 .mdiv = REG_VAL(0x24, 20, 8),
123 .ndiv_int = REG_VAL(0x4, 16, 10),
124 .pdiv = REG_VAL(0x4, 26, 4),
126 .status = REG_VAL(0x18, 12, 1),
134 .mdiv = REG_VAL(0x8, 0, 8),
140 .mdiv = REG_VAL(0x8, 10, 8),
146 .mdiv = REG_VAL(0x8, 20, 8),
152 .mdiv = REG_VAL(0xc, 0, 8),
158 .mdiv = REG_VAL(0xc, 10, 8),
164 .mdiv = REG_VAL(0xc, 20, 8),
200 .ndiv_int = REG_VAL(0x10, 20, 10),
201 .ndiv_frac = REG_VAL(0x10, 0, 20),
202 .pdiv = REG_VAL(0x14, 0, 4),
204 .status = REG_VAL(0x28, 12, 1),
212 .mdiv = REG_VAL(0x20, 0, 8),
218 .mdiv = REG_VAL(0x20, 10, 8),
224 .mdiv = REG_VAL(0x20, 20, 8),
230 .mdiv = REG_VAL(0x24, 0, 8),
236 .mdiv = REG_VAL(0x24, 10, 8),
242 .mdiv = REG_VAL(0x24, 20, 8),
/linux-4.4.14/arch/metag/kernel/
H A Dcore_reg.c27 #define REG_VAL(x) (((x) << REG_SHIFTS) & REG_BIT_MASK) macro
62 val = UNIT_VAL(unit) | REG_VAL(reg) | THREAD_VAL(thread); core_reg_write()
102 val = (UNIT_VAL(unit) | REG_VAL(reg) | THREAD_VAL(thread) | core_reg_read()

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