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Searched refs:REG_SET_BIT (Results 1 – 17 of 17) sorted by relevance

/linux-4.4.14/drivers/net/wireless/ath/ath9k/
Dar9002_phy.c287 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9, in ar9002_olc_init()
486 REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA); in ar9002_hw_spectral_scan_config()
487 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE); in ar9002_hw_spectral_scan_config()
490 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9002_hw_spectral_scan_config()
521 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE); in ar9002_hw_spectral_scan_trigger()
523 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9002_hw_spectral_scan_trigger()
542 REG_SET_BIT(ah, 0x9864, 0x7f000); in ar9002_hw_tx99_start()
543 REG_SET_BIT(ah, 0x9924, 0x7f00fe); in ar9002_hw_tx99_start()
552 REG_SET_BIT(ah, AR_QMISC(qnum), AR_Q_MISC_DCU_EARLY_TERM_REQ); in ar9002_hw_tx99_start()
557 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); in ar9002_hw_tx99_stop()
Dar9003_wow.c34 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_hw_set_sta_powersave()
133 REG_SET_BIT(ah, AR_WOW_PATTERN, BIT(pattern_count)); in ath9k_hw_wow_apply_pattern()
135 REG_SET_BIT(ah, AR_MAC_PCU_WOW4, BIT(pattern_count - 8)); in ath9k_hw_wow_apply_pattern()
312 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PMCTRL_HOST_PME_EN | in ath9k_hw_wow_enable()
326 REG_SET_BIT(ah, AR_WOW_PATTERN, in ath9k_hw_wow_enable()
332 REG_SET_BIT(ah, AR_WOW_COUNT, AR_WOW_AIFS_CNT(AR_WOW_CNT_AIFS_CNT) | in ath9k_hw_wow_enable()
387 REG_SET_BIT(ah, AR_WOW_BCN_EN, AR_WOW_BEACON_FAIL_EN); in ath9k_hw_wow_enable()
441 REG_SET_BIT(ah, AR_PCIE_PHY_REG3, BIT(13)); in ath9k_hw_wow_enable()
Dar9002_calib.c74 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_setup_calibration()
256 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_iqcalibrate()
449 REG_SET_BIT(ah, 0x9808, 1 << 27); in ar9271_hw_pa_cal()
451 REG_SET_BIT(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC); in ar9271_hw_pa_cal()
453 REG_SET_BIT(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1); in ar9271_hw_pa_cal()
455 REG_SET_BIT(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I); in ar9271_hw_pa_cal()
457 REG_SET_BIT(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF); in ar9271_hw_pa_cal()
520 REG_SET_BIT(ah, AR9285_AN_RF2G6, 1 << 0); in ar9271_hw_pa_cal()
719 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); in ar9285_hw_cl_cal()
721 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); in ar9285_hw_cl_cal()
[all …]
Dmac.c148 REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); in ath9k_hw_abort_tx_dma()
149 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); in ath9k_hw_abort_tx_dma()
150 REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); in ath9k_hw_abort_tx_dma()
413 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_FSP_CBR | in ath9k_hw_resettxqueue()
429 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_RDYTIME_EXP_POLICY); in ath9k_hw_resettxqueue()
432 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS); in ath9k_hw_resettxqueue()
437 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_FRAG_BKOFF_EN); in ath9k_hw_resettxqueue()
443 REG_SET_BIT(ah, AR_QMISC(q), in ath9k_hw_resettxqueue()
448 REG_SET_BIT(ah, AR_DMISC(q), in ath9k_hw_resettxqueue()
471 REG_SET_BIT(ah, AR_QMISC(q), in ath9k_hw_resettxqueue()
[all …]
Dhw.c731 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); in ar9003_get_pll_sqsum_dvc()
828 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); in ath9k_hw_init_pll()
1034 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); in ath9k_hw_init_global_settings()
1167 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); in ath9k_hw_set_dma()
1240 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); in ath9k_hw_set_operating_mode()
1646 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, in ath9k_hw_init_mfp()
1906 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); in ath9k_hw_reset()
1956 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, in ath9k_hw_reset()
1960 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, in ath9k_hw_reset()
1964 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); in ath9k_hw_reset()
[all …]
Dar9003_phy.c696 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ar9003_hw_set_chain_masks()
720 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); in ar9003_hw_override_ini()
1166 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control()
1495 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar9003_hw_set_radar_params()
1650 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_set_bt_ant_diversity()
1652 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_set_bt_ant_diversity()
1654 REG_SET_BIT(ah, AR_PHY_CCK_DETECT, in ar9003_hw_set_bt_ant_diversity()
1656 REG_SET_BIT(ah, AR_PHY_RESTART, in ar9003_hw_set_bt_ant_diversity()
1658 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, in ar9003_hw_set_bt_ant_diversity()
1765 REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA); in ar9003_hw_spectral_scan_config()
[all …]
Dar9002_hw.c322 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); in ar9002_hw_configpcipowersave()
376 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, in ar9002_hw_enable_async_fifo()
378 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO); in ar9002_hw_enable_async_fifo()
381 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, in ar9002_hw_enable_async_fifo()
Dcalib.c224 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, in ath9k_hw_start_nfcal()
231 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, in ath9k_hw_start_nfcal()
234 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); in ath9k_hw_start_nfcal()
274 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); in ath9k_hw_loadnf()
Dar9003_mci.c448 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); in ar9003_mci_observation_set_up()
452 REG_SET_BIT(ah, AR_GLB_GPIO_CONTROL, ATH_MCI_CONFIG_MCI_OBS_GPIO); in ar9003_mci_observation_set_up()
765 REG_SET_BIT(ah, AR_PHY_TIMING4, in ar9003_mci_end_reset()
783 REG_SET_BIT(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE); in ar9003_mci_mute_bt()
946 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, in ar9003_mci_reset()
971 REG_SET_BIT(ah, AR_BTCOEX_CTRL, AR_BTCOEX_CTRL_MCI_MODE_EN); in ar9003_mci_reset()
1008 REG_SET_BIT(ah, AR_MCI_TX_CTRL, in ar9003_mci_reset()
1145 REG_SET_BIT(ah, AR_MCI_TX_CTRL, in ar9003_mci_2g5g_switch()
1147 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, in ar9003_mci_2g5g_switch()
1403 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL); in ar9003_mci_bt_gain_ctrl()
[all …]
Dar9003_aic.c255 REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_CH_VALID_RESET); in ar9003_aic_cal_start()
256 REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE); in ar9003_aic_cal_start()
509 REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1, in ar9003_aic_cal_continue()
511 REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE); in ar9003_aic_cal_continue()
Dar9003_calib.c59 REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL); in ar9003_hw_setup_calibration()
301 REG_SET_BIT(ah, AR_PHY_RX_IQCAL_CORR_B0, in ar9003_hw_iqcalibrate()
371 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_dynamic_osdac_selection()
389 REG_SET_BIT(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); in ar9003_hw_dynamic_osdac_selection()
537 REG_SET_BIT(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); in ar9003_hw_dynamic_osdac_selection()
543 REG_SET_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0, in ar9003_hw_dynamic_osdac_selection()
1435 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, in ar9003_hw_init_cal_pcoem()
1456 REG_SET_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0, in ar9003_hw_init_cal_pcoem()
1598 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); in ar9003_hw_init_cal_soc()
Dar5008_phy.c587 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ar5008_hw_init_chain_masks()
612 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ar5008_hw_init_chain_masks()
630 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); in ar5008_hw_override_ini()
766 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENA); in ar5008_hw_process_ini()
1008 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, in ar5008_hw_ani_control_new()
1244 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar5008_hw_set_radar_params()
Dbtcoex.c136 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, in ath9k_hw_btcoex_init_2wire()
154 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, in ath9k_hw_btcoex_init_3wire()
Dar9003_paprd.c942 REG_SET_BIT(ah, AR_PHY_CHAN_INFO_MEMORY, in ar9003_paprd_create_curve()
Dhw.h127 #define REG_SET_BIT(_a, _r, _f) \ macro
Dar9003_hw.c1032 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); in ar9003_hw_configpcipowersave()
Dar9003_eeprom.c3627 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_SPDT_ENABLE); in ar9003_hw_ant_ctrl_apply()
3674 REG_SET_BIT(ah, AR_PHY_RESTART, in ar9003_hw_ant_ctrl_apply()
3678 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, in ar9003_hw_ant_ctrl_apply()