Searched refs:REG_OFFSET (Results 1 - 21 of 21) sorted by relevance

/linux-4.4.14/arch/arm64/kvm/
H A Dregmap.c28 #define REG_OFFSET(_reg) \ macro
31 #define USR_REG_OFFSET(R) REG_OFFSET(compat_usr(R))
41 REG_OFFSET(pc)
49 REG_OFFSET(compat_r8_fiq), /* r8 */
50 REG_OFFSET(compat_r9_fiq), /* r9 */
51 REG_OFFSET(compat_r10_fiq), /* r10 */
52 REG_OFFSET(compat_r11_fiq), /* r11 */
53 REG_OFFSET(compat_r12_fiq), /* r12 */
54 REG_OFFSET(compat_sp_fiq), /* r13 */
55 REG_OFFSET(compat_lr_fiq), /* r14 */
56 REG_OFFSET(pc)
66 REG_OFFSET(compat_sp_irq), /* r13 */
67 REG_OFFSET(compat_lr_irq), /* r14 */
68 REG_OFFSET(pc)
78 REG_OFFSET(compat_sp_svc), /* r13 */
79 REG_OFFSET(compat_lr_svc), /* r14 */
80 REG_OFFSET(pc)
90 REG_OFFSET(compat_sp_abt), /* r13 */
91 REG_OFFSET(compat_lr_abt), /* r14 */
92 REG_OFFSET(pc)
102 REG_OFFSET(compat_sp_und), /* r13 */
103 REG_OFFSET(compat_lr_und), /* r14 */
104 REG_OFFSET(pc)
/linux-4.4.14/drivers/gpu/drm/gma500/
H A Dmdfld_dsi_output.h86 #define REG_OFFSET(pipe) (CHECK_PIPE(pipe) * 0x400) macro
89 #define MIPI_DEVICE_READY_REG(pipe) (0xb000 + REG_OFFSET(pipe))
90 #define MIPI_INTR_STAT_REG(pipe) (0xb004 + REG_OFFSET(pipe))
91 #define MIPI_INTR_EN_REG(pipe) (0xb008 + REG_OFFSET(pipe))
92 #define MIPI_DSI_FUNC_PRG_REG(pipe) (0xb00c + REG_OFFSET(pipe))
93 #define MIPI_HS_TX_TIMEOUT_REG(pipe) (0xb010 + REG_OFFSET(pipe))
94 #define MIPI_LP_RX_TIMEOUT_REG(pipe) (0xb014 + REG_OFFSET(pipe))
95 #define MIPI_TURN_AROUND_TIMEOUT_REG(pipe) (0xb018 + REG_OFFSET(pipe))
96 #define MIPI_DEVICE_RESET_TIMER_REG(pipe) (0xb01c + REG_OFFSET(pipe))
97 #define MIPI_DPI_RESOLUTION_REG(pipe) (0xb020 + REG_OFFSET(pipe))
98 #define MIPI_DBI_FIFO_THROTTLE_REG(pipe) (0xb024 + REG_OFFSET(pipe))
99 #define MIPI_HSYNC_COUNT_REG(pipe) (0xb028 + REG_OFFSET(pipe))
100 #define MIPI_HBP_COUNT_REG(pipe) (0xb02c + REG_OFFSET(pipe))
101 #define MIPI_HFP_COUNT_REG(pipe) (0xb030 + REG_OFFSET(pipe))
102 #define MIPI_HACTIVE_COUNT_REG(pipe) (0xb034 + REG_OFFSET(pipe))
103 #define MIPI_VSYNC_COUNT_REG(pipe) (0xb038 + REG_OFFSET(pipe))
104 #define MIPI_VBP_COUNT_REG(pipe) (0xb03c + REG_OFFSET(pipe))
105 #define MIPI_VFP_COUNT_REG(pipe) (0xb040 + REG_OFFSET(pipe))
106 #define MIPI_HIGH_LOW_SWITCH_COUNT_REG(pipe) (0xb044 + REG_OFFSET(pipe))
107 #define MIPI_DPI_CONTROL_REG(pipe) (0xb048 + REG_OFFSET(pipe))
108 #define MIPI_DPI_DATA_REG(pipe) (0xb04c + REG_OFFSET(pipe))
109 #define MIPI_INIT_COUNT_REG(pipe) (0xb050 + REG_OFFSET(pipe))
110 #define MIPI_MAX_RETURN_PACK_SIZE_REG(pipe) (0xb054 + REG_OFFSET(pipe))
111 #define MIPI_VIDEO_MODE_FORMAT_REG(pipe) (0xb058 + REG_OFFSET(pipe))
112 #define MIPI_EOT_DISABLE_REG(pipe) (0xb05c + REG_OFFSET(pipe))
113 #define MIPI_LP_BYTECLK_REG(pipe) (0xb060 + REG_OFFSET(pipe))
114 #define MIPI_LP_GEN_DATA_REG(pipe) (0xb064 + REG_OFFSET(pipe))
115 #define MIPI_HS_GEN_DATA_REG(pipe) (0xb068 + REG_OFFSET(pipe))
116 #define MIPI_LP_GEN_CTRL_REG(pipe) (0xb06c + REG_OFFSET(pipe))
117 #define MIPI_HS_GEN_CTRL_REG(pipe) (0xb070 + REG_OFFSET(pipe))
118 #define MIPI_GEN_FIFO_STAT_REG(pipe) (0xb074 + REG_OFFSET(pipe))
119 #define MIPI_HS_LS_DBI_ENABLE_REG(pipe) (0xb078 + REG_OFFSET(pipe))
120 #define MIPI_DPHY_PARAM_REG(pipe) (0xb080 + REG_OFFSET(pipe))
121 #define MIPI_DBI_BW_CTRL_REG(pipe) (0xb084 + REG_OFFSET(pipe))
122 #define MIPI_CLK_LANE_SWITCH_TIME_CNT_REG(pipe) (0xb088 + REG_OFFSET(pipe))
124 #define MIPI_CTRL_REG(pipe) (0xb104 + REG_OFFSET(pipe))
125 #define MIPI_DATA_ADD_REG(pipe) (0xb108 + REG_OFFSET(pipe))
126 #define MIPI_DATA_LEN_REG(pipe) (0xb10c + REG_OFFSET(pipe))
127 #define MIPI_CMD_ADD_REG(pipe) (0xb110 + REG_OFFSET(pipe))
128 #define MIPI_CMD_LEN_REG(pipe) (0xb114 + REG_OFFSET(pipe))
/linux-4.4.14/arch/arm/kvm/
H A Demulate.c35 #define REG_OFFSET(_reg) \ macro
38 #define USR_REG_OFFSET(_num) REG_OFFSET(usr_regs.uregs[_num])
55 REG_OFFSET(fiq_regs[0]), /* r8 */
56 REG_OFFSET(fiq_regs[1]), /* r9 */
57 REG_OFFSET(fiq_regs[2]), /* r10 */
58 REG_OFFSET(fiq_regs[3]), /* r11 */
59 REG_OFFSET(fiq_regs[4]), /* r12 */
60 REG_OFFSET(fiq_regs[5]), /* r13 */
61 REG_OFFSET(fiq_regs[6]), /* r14 */
71 REG_OFFSET(irq_regs[0]), /* r13 */
72 REG_OFFSET(irq_regs[1]), /* r14 */
82 REG_OFFSET(svc_regs[0]), /* r13 */
83 REG_OFFSET(svc_regs[1]), /* r14 */
93 REG_OFFSET(abt_regs[0]), /* r13 */
94 REG_OFFSET(abt_regs[1]), /* r14 */
104 REG_OFFSET(und_regs[0]), /* r13 */
105 REG_OFFSET(und_regs[1]), /* r14 */
/linux-4.4.14/arch/mips/ar7/
H A Dirq.c32 #define REG_OFFSET(irq, reg) ((irq) / 32 * 0x4 + reg * 0x10) macro
35 #define CR_OFFSET(irq) (REG_OFFSET(irq, 1)) /* 0x10 */
37 #define ESR_OFFSET(irq) (REG_OFFSET(irq, 2)) /* 0x20 */
39 #define ECR_OFFSET(irq) (REG_OFFSET(irq, 3)) /* 0x30 */
43 #define PM_OFFSET(irq) (REG_OFFSET(irq, 5)) /* 0x50 */
44 #define TM_OFFSET(irq) (REG_OFFSET(irq, 6)) /* 0x60 */
/linux-4.4.14/arch/arm/mach-ixp4xx/
H A Dcoyote-setup.c64 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
101 (char*)(IXP4XX_UART1_BASE_VIRT + REG_OFFSET); coyote_init()
H A Dgtwx5715-setup.c83 #define REG_OFFSET 3 macro
85 #define REG_OFFSET 0 macro
110 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
H A Davila-setup.c81 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
90 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
H A Dvulcan-setup.c80 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
89 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
H A Dgateway7001-setup.c58 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
H A Dwg302v2-setup.c59 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
H A Dfsg-setup.c92 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
101 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
H A Dixdp425-setup.c154 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
163 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
H A Domixp-setup.c128 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
136 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
H A Ddsmg600-setup.c130 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
139 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
H A Dnas100d-setup.c132 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
141 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
H A Dnslu2-setup.c144 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
153 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
H A Dgoramo_mlr.c251 REG_OFFSET,
261 REG_OFFSET,
/linux-4.4.14/arch/arm/mach-ixp4xx/include/mach/
H A Dplatform.h21 #define REG_OFFSET 0 macro
23 #define REG_OFFSET 3 macro
/linux-4.4.14/arch/ia64/hp/sim/boot/
H A Dfw-emu.c106 #define REG_OFFSET(addr) (0x00000000000000FF & (addr)) macro
202 r9 = inb(0xCFC + ((REG_OFFSET(in1) & 3))); sal_emulator()
204 r9 = inw(0xCFC + ((REG_OFFSET(in1) & 2))); sal_emulator()
216 outb(in3, 0xCFC + ((REG_OFFSET(in1) & 3))); sal_emulator()
218 outw(in3, 0xCFC + ((REG_OFFSET(in1) & 2))); sal_emulator()
/linux-4.4.14/drivers/pinctrl/spear/
H A Dpinctrl-plgpio.c26 #define REG_OFFSET(base, reg, pin) (base + reg + (pin / MAX_GPIO_PER_REG) \ macro
83 void __iomem *reg_off = REG_OFFSET(base, reg, pin); is_plgpio_set()
92 void __iomem *reg_off = REG_OFFSET(base, reg, pin); plgpio_reg_set()
101 void __iomem *reg_off = REG_OFFSET(base, reg, pin); plgpio_reg_reset()
340 reg_off = REG_OFFSET(plgpio->base, plgpio->regs.eit, offset); plgpio_irq_set_type()
/linux-4.4.14/sound/soc/sh/
H A Dsiu_dai.c49 #define REG_OFFSET 0xc000 macro
781 info->reg = devm_ioremap(&pdev->dev, res->start + REG_OFFSET, siu_probe()
782 resource_size(res) - REG_OFFSET); siu_probe()

Completed in 377 milliseconds