Searched refs:REG_BASE_ADDR (Results 1 - 3 of 3) sorted by relevance

/linux-4.4.14/drivers/scsi/aic94xx/
H A Daic94xx_reg_def.h46 /* The base is REG_BASE_ADDR, defined in aic94xx_reg.h.
52 #define COMBIST (REG_BASE_ADDR + 0x00)
81 #define COMSTAT (REG_BASE_ADDR + 0x04)
94 #define COMSTATEN (REG_BASE_ADDR + 0x08)
103 #define SCBPRO (REG_BASE_ADDR + 0x0C)
108 #define CHIMREQMBX (REG_BASE_ADDR + 0x10)
110 #define CHIMRSPMBX (REG_BASE_ADDR + 0x14)
112 #define CHIMINT (REG_BASE_ADDR + 0x18)
132 #define CHIMINTEN (REG_BASE_ADDR + 0x1C)
162 #define OVLYDMACTL (REG_BASE_ADDR + 0x20)
174 #define OVLYDMACNT (REG_BASE_ADDR + 0x24)
181 #define OVLYDMAADR (REG_BASE_ADDR + 0x28)
183 #define DMAERR (REG_BASE_ADDR + 0x30)
188 #define SPIODATA (REG_BASE_ADDR + 0x34)
192 #define T1CNTRLR (REG_BASE_ADDR + 0x40)
200 #define T1CMPR (REG_BASE_ADDR + 0x44)
202 #define T1CNTR (REG_BASE_ADDR + 0x48)
204 #define T2CNTRLR (REG_BASE_ADDR + 0x4C)
211 #define T2CMPR (REG_BASE_ADDR + 0x50)
213 #define T2CNTR (REG_BASE_ADDR + 0x54)
220 #define CMDCTXBASE (REG_BASE_ADDR + 0x800)
222 #define DEVCTXBASE (REG_BASE_ADDR + 0x808)
224 #define CTXDOMAIN (REG_BASE_ADDR + 0x810)
231 #define DCHCTL (REG_BASE_ADDR + 0x814)
255 #define DCHREVISION (REG_BASE_ADDR + 0x818)
259 #define DCHSTATUS (REG_BASE_ADDR + 0x81C)
277 #define DCHDFIFDEBUG (REG_BASE_ADDR + 0x820)
283 #define ATOMICSTATCTL (REG_BASE_ADDR + 0x824)
291 #define ALTCIOADR (REG_BASE_ADDR + 0x828)
294 #define ASCBPTR (REG_BASE_ADDR + 0x82C)
297 #define ADDBPTR (REG_BASE_ADDR + 0x82E)
300 #define ANEWDATA (REG_BASE_ADDR + 0x830)
303 #define AOLDDATA (REG_BASE_ADDR + 0x834)
306 #define CTXACCESS (REG_BASE_ADDR + 0x838)
H A Daic94xx_reg.h37 #define REG_BASE_ADDR 0xB8000000 macro
H A Daic94xx_hwi.c185 pci_write_config_dword(pcidev, PCI_CONF_MBAR0_SWA, REG_BASE_ADDR); asd_init_sw()
189 asd_ha->io_handle[0].swa_base = REG_BASE_ADDR; asd_init_sw()

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