Searched refs:REGBASE (Results 1 - 7 of 7) sorted by relevance

/linux-4.4.14/arch/mips/include/asm/emma/
H A Demma2rh.h29 #define REGBASE 0x10000000 macro
31 #define EMMA2RH_BHIF_STRAP_0 (0x000010+REGBASE)
32 #define EMMA2RH_BHIF_INT_ST_0 (0x000030+REGBASE)
33 #define EMMA2RH_BHIF_INT_ST_1 (0x000034+REGBASE)
34 #define EMMA2RH_BHIF_INT_ST_2 (0x000038+REGBASE)
35 #define EMMA2RH_BHIF_INT_EN_0 (0x000040+REGBASE)
36 #define EMMA2RH_BHIF_INT_EN_1 (0x000044+REGBASE)
37 #define EMMA2RH_BHIF_INT_EN_2 (0x000048+REGBASE)
38 #define EMMA2RH_BHIF_INT1_EN_0 (0x000050+REGBASE)
39 #define EMMA2RH_BHIF_INT1_EN_1 (0x000054+REGBASE)
40 #define EMMA2RH_BHIF_INT1_EN_2 (0x000058+REGBASE)
41 #define EMMA2RH_BHIF_SW_INT (0x000070+REGBASE)
42 #define EMMA2RH_BHIF_SW_INT_EN (0x000080+REGBASE)
43 #define EMMA2RH_BHIF_SW_INT_CLR (0x000090+REGBASE)
44 #define EMMA2RH_BHIF_MAIN_CTRL (0x0000b4+REGBASE)
45 #define EMMA2RH_BHIF_EXCEPT_VECT_BASE_ADDRESS (0x0000c0+REGBASE)
46 #define EMMA2RH_GPIO_DIR (0x110d20+REGBASE)
47 #define EMMA2RH_GPIO_INT_ST (0x110d30+REGBASE)
48 #define EMMA2RH_GPIO_INT_MASK (0x110d3c+REGBASE)
49 #define EMMA2RH_GPIO_INT_MODE (0x110d48+REGBASE)
50 #define EMMA2RH_GPIO_INT_CND_A (0x110d54+REGBASE)
51 #define EMMA2RH_GPIO_INT_CND_B (0x110d60+REGBASE)
52 #define EMMA2RH_PBRD_INT_EN (0x100010+REGBASE)
53 #define EMMA2RH_PBRD_CLKSEL (0x100028+REGBASE)
54 #define EMMA2RH_PFUR0_BASE (0x101000+REGBASE)
55 #define EMMA2RH_PFUR1_BASE (0x102000+REGBASE)
56 #define EMMA2RH_PFUR2_BASE (0x103000+REGBASE)
57 #define EMMA2RH_PIIC0_BASE (0x107000+REGBASE)
58 #define EMMA2RH_PIIC1_BASE (0x108000+REGBASE)
59 #define EMMA2RH_PIIC2_BASE (0x109000+REGBASE)
60 #define EMMA2RH_PCI_CONTROL (0x200000+REGBASE)
61 #define EMMA2RH_PCI_ARBIT_CTR (0x200004+REGBASE)
62 #define EMMA2RH_PCI_IWIN0_CTR (0x200010+REGBASE)
63 #define EMMA2RH_PCI_IWIN1_CTR (0x200014+REGBASE)
64 #define EMMA2RH_PCI_INIT_ESWP (0x200018+REGBASE)
65 #define EMMA2RH_PCI_INT (0x200020+REGBASE)
66 #define EMMA2RH_PCI_INT_EN (0x200024+REGBASE)
67 #define EMMA2RH_PCI_TWIN_CTR (0x200030+REGBASE)
68 #define EMMA2RH_PCI_TWIN_BADR (0x200034+REGBASE)
69 #define EMMA2RH_PCI_TWIN0_DADR (0x200038+REGBASE)
70 #define EMMA2RH_PCI_TWIN1_DADR (0x20003c+REGBASE)
/linux-4.4.14/arch/mips/include/asm/mach-rc32434/
H A Dirq.h10 #define IC_GROUP0_PEND (REGBASE + 0x38000)
11 #define IC_GROUP0_MASK (REGBASE + 0x38008)
H A Drb.h20 #define REGBASE 0x18000000 macro
21 #define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(REGBASE))
/linux-4.4.14/drivers/net/wan/
H A Dwanxlfw.S90 REGBASE = DPRBASE + 0x1000 define
91 PICR = REGBASE + 0x026 // 16-bit periodic irq control
92 PITR = REGBASE + 0x02A // 16-bit periodic irq timing
93 OR1 = REGBASE + 0x064 // 32-bit RAM bank #1 options
94 CICR = REGBASE + 0x540 // 32(24)-bit CP interrupt config
95 CIMR = REGBASE + 0x548 // 32-bit CP interrupt mask
96 CISR = REGBASE + 0x54C // 32-bit CP interrupts in-service
97 PADIR = REGBASE + 0x550 // 16-bit PortA data direction bitmap
98 PAPAR = REGBASE + 0x552 // 16-bit PortA pin assignment bitmap
99 PAODR = REGBASE + 0x554 // 16-bit PortA open drain bitmap
100 PADAT = REGBASE + 0x556 // 16-bit PortA data register
102 PCDIR = REGBASE + 0x560 // 16-bit PortC data direction bitmap
103 PCPAR = REGBASE + 0x562 // 16-bit PortC pin assignment bitmap
104 PCSO = REGBASE + 0x564 // 16-bit PortC special options
105 PCDAT = REGBASE + 0x566 // 16-bit PortC data register
106 PCINT = REGBASE + 0x568 // 16-bit PortC interrupt control
107 CR = REGBASE + 0x5C0 // 16-bit Command register
109 SCC1_REGS = REGBASE + 0x600
110 SCC2_REGS = REGBASE + 0x620
111 SCC3_REGS = REGBASE + 0x640
112 SCC4_REGS = REGBASE + 0x660
113 SICR = REGBASE + 0x6EC // 32-bit SI clock route
/linux-4.4.14/arch/mips/rb532/
H A Dserial.c44 .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
H A Dgpio.c48 .start = REGBASE + GPIOBASE,
49 .end = REGBASE + GPIOBASE + sizeof(struct rb532_gpio_reg) - 1,
H A Ddevices.c228 .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),

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