Searched refs:PXA1928_CLK_SDH0 (Results 1 - 8 of 8) sorted by relevance

/linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/clock/
H A Dmarvell,pxa1928.h42 #define PXA1928_CLK_SDH0 0x15 macro
/linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/clock/
H A Dmarvell,pxa1928.h42 #define PXA1928_CLK_SDH0 0x15 macro
/linux-4.4.14/include/dt-bindings/clock/
H A Dmarvell,pxa1928.h42 #define PXA1928_CLK_SDH0 0x15 macro
/linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/clock/
H A Dmarvell,pxa1928.h42 #define PXA1928_CLK_SDH0 0x15 macro
/linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/clock/
H A Dmarvell,pxa1928.h42 #define PXA1928_CLK_SDH0 0x15 macro
/linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/clock/
H A Dmarvell,pxa1928.h42 #define PXA1928_CLK_SDH0 0x15 macro
/linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/clock/
H A Dmarvell,pxa1928.h42 #define PXA1928_CLK_SDH0 0x15 macro
/linux-4.4.14/drivers/clk/mmp/
H A Dclk-of-pxa1928.c152 {0, "sdh_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_SDH0 * 4, 8, 2, 0, &sdh0_lock},
156 {0, "sdh_div", "sdh_mux", 0, PXA1928_CLK_SDH0 * 4, 10, 4, CLK_DIVIDER_ONE_BASED, &sdh0_lock},
163 {PXA1928_CLK_SDH0, "sdh0_clk", "sdh_div", CLK_SET_RATE_PARENT, PXA1928_CLK_SDH0 * 4, 0x1b, 0x1b, 0x0, 0, &sdh0_lock},

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