Searched refs:PPLL_REF_DIV (Results 1 – 5 of 5) sorted by relevance
631 switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) { in radeon_probe_pll_params()655 m = (INPLL(PPLL_REF_DIV) & 0x3ff); in radeon_probe_pll_params()697 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff; in radeon_probe_pll_params()776 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; in radeon_get_pllinfo()1357 save->ppll_ref_div = INPLL(PPLL_REF_DIV); in radeon_save_state()1376 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && in radeon_write_pll_regs()1415 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0); in radeon_write_pll_regs()1418 OUTPLLP(PPLL_REF_DIV, in radeon_write_pll_regs()1423 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK); in radeon_write_pll_regs()1430 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R) in radeon_write_pll_regs()[all …]
592 return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); in aty_pll_readupdate()617 aty_st_pll(PPLL_REF_DIV, in aty_pll_writeupdate()618 aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W); in aty_pll_writeupdate()983 aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; in aty128_timings()992 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider); in aty128_timings()1348 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff); in aty128_set_pll()
2448 tmp = INPLL(PPLL_REF_DIV);2450 OUTPLL(PPLL_REF_DIV, tmp);2451 INPLL(PPLL_REF_DIV);
243 #define PPLL_REF_DIV 0x0003 macro
430 #define PPLL_REF_DIV 0x0003 macro