| /linux-4.4.14/arch/blackfin/mach-common/ |
| D | dpmc_modes.S | 106 P0.H = hi(PLL_DIV);
107 P0.L = lo(PLL_DIV);
171 P0.H = hi(PLL_DIV);
172 P0.L = lo(PLL_DIV);
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| /linux-4.4.14/drivers/mfd/ |
| D | db8500-prcmu.c | 462 PLL_DIV enumerator
470 CLK_MGT_ENTRY(SGACLK, PLL_DIV, false),
475 CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true),
477 CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true),
478 CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true),
479 CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true),
480 CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true),
481 CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
482 CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
484 CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
[all …]
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| /linux-4.4.14/arch/mips/ar7/ |
| D | clock.c | 67 #define PLL_DIV 0x00000002 macro
205 if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) { in tnetd7300_get_clock()
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| /linux-4.4.14/drivers/clk/at91/ |
| D | clk-pll.c | 30 #define PLL_DIV(reg) ((reg) & PLL_DIV_MASK) macro
98 div = PLL_DIV(pllr); in clk_pll_prepare()
343 pll->div = PLL_DIV(tmp); in at91_clk_register_pll()
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| /linux-4.4.14/arch/blackfin/mach-bf533/include/mach/ |
| D | defBF532.h | 18 #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ macro
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| D | cdefBF532.h | 17 #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
18 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
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| /linux-4.4.14/arch/blackfin/mach-bf518/include/mach/ |
| D | defBF512.h | 16 #define PLL_DIV 0xFFC00004 /* PLL Divide Register */ macro
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| D | cdefBF512.h | 12 #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
13 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
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| /linux-4.4.14/arch/blackfin/mach-bf527/include/mach/ |
| D | defBF522.h | 18 #define PLL_DIV 0xFFC00004 /* PLL Divide Register */ macro
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| D | cdefBF522.h | 12 #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
13 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
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| /linux-4.4.14/arch/blackfin/mach-bf561/include/mach/ |
| D | defBF561.h | 17 #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ macro
|
| D | cdefBF561.h | 16 #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
17 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
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| /linux-4.4.14/arch/blackfin/mach-bf537/include/mach/ |
| D | defBF534.h | 15 #define PLL_DIV 0xFFC00004 /* PLL Divide Register */ macro
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| D | cdefBF534.h | 12 #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
13 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
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| /linux-4.4.14/arch/blackfin/mach-bf538/include/mach/ |
| D | defBF538.h | 12 #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ macro
|
| D | cdefBF538.h | 13 #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
14 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
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| /linux-4.4.14/arch/blackfin/mach-bf548/include/mach/ |
| D | defBF54x_base.h | 18 #define PLL_DIV 0xffc00004 /* PLL Divisor Register */ macro
|
| D | cdefBF54x_base.h | 17 #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
18 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
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| /linux-4.4.14/arch/blackfin/kernel/ |
| D | debug-mmrs.c | 1333 D16(PLL_DIV); in bfin_debug_mmrs_init()
|