Searched refs:PLLCTL (Results 1 - 8 of 8) sorted by relevance

/linux-4.4.14/arch/arm/mach-davinci/
H A Dpm.c47 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); davinci_pm_suspend()
49 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); davinci_pm_suspend()
54 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); davinci_pm_suspend()
56 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); davinci_pm_suspend()
71 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); davinci_pm_suspend()
73 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); davinci_pm_suspend()
76 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); davinci_pm_suspend()
78 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); davinci_pm_suspend()
84 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); davinci_pm_suspend()
86 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); davinci_pm_suspend()
92 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); davinci_pm_suspend()
95 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); davinci_pm_suspend()
H A Dsleep.S90 ldr ip, [r3, #PLLCTL]
93 str ip, [r3, #PLLCTL]
101 ldr ip, [r3, #PLLCTL]
103 str ip, [r3, #PLLCTL]
121 ldr ip, [r3, #PLLCTL]
123 str ip, [r3, #PLLCTL]
126 ldr ip, [r3, #PLLCTL]
128 str ip, [r3, #PLLCTL]
135 ldr ip, [r3, #PLLCTL]
137 str ip, [r3, #PLLCTL]
145 ldr ip, [r3, #PLLCTL]
148 str ip, [r3, #PLLCTL]
H A Dclock.c421 ctrl = __raw_readl(pll->base + PLLCTL); clk_pllclk_recalc()
514 ctrl = __raw_readl(pll->base + PLLCTL); davinci_set_pllrate()
518 __raw_writel(ctrl, pll->base + PLLCTL); davinci_set_pllrate()
524 __raw_writel(ctrl, pll->base + PLLCTL); davinci_set_pllrate()
538 __raw_writel(ctrl, pll->base + PLLCTL); davinci_set_pllrate()
544 __raw_writel(ctrl, pll->base + PLLCTL); davinci_set_pllrate()
H A Dclock.h20 #define PLLCTL 0x100 macro
/linux-4.4.14/arch/c6x/include/asm/
H A Dclock.h25 #define PLLCTL 0x100 macro
61 /* PLLCTL register bits */
/linux-4.4.14/arch/c6x/platforms/
H A Dpll.c279 ctrl = pll_read(pll, PLLCTL); clk_pllclk_recalc()
/linux-4.4.14/sound/pci/ctxfi/
H A Dct20k1reg.h615 #define PLLCTL 0x1C6060 macro
H A Dcthw20k1.c1324 if (hw_read_20kx(hw, PLLCTL) == pllctl) hw_pll_init()
1327 hw_write_20kx(hw, PLLCTL, pllctl); hw_pll_init()
1973 data = hw_read_20kx(hw, PLLCTL); hw_card_stop()
1974 hw_write_20kx(hw, PLLCTL, (data & (~(0x0F<<12)))); hw_card_stop()

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