| /linux-4.4.14/arch/sh/kernel/cpu/sh2a/ |
| H A D | setup-mxg.c | 23 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, enumerator in enum:__anon2622
45 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
83 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
111 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
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| H A D | setup-sh7201.c | 23 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, enumerator in enum:__anon2623
58 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
149 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
174 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
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| H A D | setup-sh7203.c | 22 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, enumerator in enum:__anon2624
51 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
135 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
170 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
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| H A D | setup-sh7206.c | 23 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, enumerator in enum:__anon2625
49 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
104 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
130 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
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| H A D | setup-sh7264.c | 23 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, enumerator in enum:__anon2626
57 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
180 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
222 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
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| H A D | setup-sh7269.c | 24 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, enumerator in enum:__anon2627
61 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
197 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
244 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
|
| /linux-4.4.14/arch/blackfin/mach-bf609/include/mach/ |
| H A D | irq.h | 38 #define IRQ_PINT1 BFIN_IRQ(22) /* PINT1 Interrupt */
|
| H A D | defBF60x_base.h | 872 PINT1
874 #define PINT1_MASK_SET 0xFFC04100 /* PINT1 Pint Mask Set Register */
875 #define PINT1_MASK_CLEAR 0xFFC04104 /* PINT1 Pint Mask Clear Register */
876 #define PINT1_REQUEST 0xFFC04108 /* PINT1 Pint Request Register */
877 #define PINT1_ASSIGN 0xFFC0410C /* PINT1 Pint Assign Register */
878 #define PINT1_EDGE_SET 0xFFC04110 /* PINT1 Pint Edge Set Register */
879 #define PINT1_EDGE_CLEAR 0xFFC04114 /* PINT1 Pint Edge Clear Register */
880 #define PINT1_INVERT_SET 0xFFC04118 /* PINT1 Pint Invert Set Register */
881 #define PINT1_INVERT_CLEAR 0xFFC0411C /* PINT1 Pint Invert Clear Register */
882 #define PINT1_PINSTATE 0xFFC04120 /* PINT1 Pint Pinstate Register */
883 #define PINT1_LATCH 0xFFC04124 /* PINT1 Pint Latch Register */
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| /linux-4.4.14/arch/blackfin/mach-bf548/include/mach/ |
| H A D | irq.h | 34 #define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */
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| H A D | defBF54x_base.h | 1533 #define PINT1 0x100000 /* Pin Interrupt 1 */ macro
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| /linux-4.4.14/drivers/pinctrl/ |
| H A D | pinctrl-adi2.c | 35 four hardware blocks, called PINT0, PINT1, PINT2, and PINT3. Every PINTx
36 block can sense to up to 32 pins. While PINT0 and PINT1 can sense the
|