| /linux-4.4.14/include/linux/platform_data/ |
| H A D | pinctrl-adi2.h | 24 * @pint_id: GPIO PINT device id that this GPIO bank should map to.
25 * @pint_assign: The 32-bit GPIO PINT registers can be divided into 2 parts. A
27 * bits[1] of each PINT register.
28 * @pint_map: GIOP bank mapping code in PINT device
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| /linux-4.4.14/arch/sh/kernel/cpu/sh2a/ |
| H A D | setup-mxg.c | 32 PINT, enumerator in enum:__anon2622
83 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
92 { 0xfffd9420, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
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| H A D | setup-sh7201.c | 49 PINT, enumerator in enum:__anon2623
149 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
156 { 0xfffe9420, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI, 0 } },
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| H A D | setup-sh7203.c | 43 PINT, enumerator in enum:__anon2624
135 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
142 { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
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| H A D | setup-sh7206.c | 41 PINT, enumerator in enum:__anon2625
104 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
111 { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI0, ADC_ADI1 } },
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| H A D | setup-sh7264.c | 48 PINT, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7, enumerator in enum:__anon2626
180 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
195 { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
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| H A D | setup-sh7269.c | 52 PINT, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7, enumerator in enum:__anon2627
197 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
212 { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
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| /linux-4.4.14/drivers/pinctrl/ |
| H A D | pinctrl-adi2.c | 53 to one PINT device. Two in "struct gpio_pint" are used to ease the PINT
56 The GPIO bank mapping to the lower 16 bits of the PINT device set its IRQ
58 to domain[1]. PINT interrupt handler adi_gpio_handle_pint_irq() finds out
62 A PINT device is not part of a GPIO port device in Blackfin. Multiple GPIO
63 port devices can be mapped to the same PINT device.
93 * struct gpio_pint_saved - PINT registers saved in PM operations
110 * @base: PINT device register base address
111 * @irq: IRQ of the PINT device, it is the parent IRQ of all
117 * @regs: address pointer to the PINT device
118 * @map_count: No more than 2 GPIO banks can be mapped to this PINT device.
119 * @lock: This lock make sure the irq_chip operations to one PINT device
121 * @pint_map_port: Set up the mapping between one PINT device and
162 * @pint: GPIO PINT device that this GPIO bank mapped to
163 * @pint_map: GIOP bank mapping code in PINT device
164 * @pint_assign: The 32-bit PINT registers can be divided into 2 parts. A
166 * bits[1] of each PINT register.
167 * @lock: This lock make sure the irq_chip operations to one PINT device
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| /linux-4.4.14/arch/sh/include/asm/ |
| H A D | irq.h | 33 * PINT IRQs
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| /linux-4.4.14/arch/sh/include/cpu-sh2a/cpu/ |
| H A D | sh7203.h | 43 /* INTC: IRQ and PINT on PB/PD/PE */
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| H A D | sh7264.h | 62 /* INTC: IRQ and PINT on PB/PD/PE */
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| H A D | sh7269.h | 64 /* INTC: IRQ and PINT */
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| /linux-4.4.14/drivers/input/mouse/ |
| H A D | navpoint.c | 67 | SSSR_PINT /* PINT = 1; Clear PINT */
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| /linux-4.4.14/drivers/sh/intc/ |
| H A D | chip.c | 189 /* PINT has 2-bit sense registers, should fail on EDGE_BOTH */ intc_set_type()
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| /linux-4.4.14/arch/blackfin/kernel/ |
| H A D | debug-mmrs.c | 330 * Peripheral Interrupts (PINT/GPIO)
337 char buf[32], *_buf = REGS_STR_PFX(buf, PINT, num); bfin_debug_mmrs_pint()
349 #define PINT(num) bfin_debug_mmrs_pint(parent, PINT##num##_MASK_SET, num) macro
1302 PINT(0); bfin_debug_mmrs_init()
1303 PINT(1); bfin_debug_mmrs_init()
1304 PINT(2); bfin_debug_mmrs_init()
1305 PINT(3); bfin_debug_mmrs_init()
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| /linux-4.4.14/arch/blackfin/mach-bf548/boards/ |
| H A D | ezkit.c | 1205 .pint_assign = true, /* PINT upper 16 bit */
1206 .pint_map = 0, /* mapping mask in PINT */
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| /linux-4.4.14/arch/blackfin/mach-bf609/boards/ |
| H A D | ezkit.c | 1500 .pint_assign = true, /* PINT upper 16 bit */
1501 .pint_map = 0, /* mapping mask in PINT */
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| /linux-4.4.14/arch/blackfin/mach-bf609/include/mach/ |
| H A D | defBF60x_base.h | 854 PINT Registers
|