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Searched refs:PINMUX_CFG_REG (Results 1 – 23 of 23) sorted by relevance

/linux-4.4.14/drivers/pinctrl/sh-pfc/
Dpfc-sh7264.c1472 { PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1) {
1482 { PINMUX_CFG_REG("PBCR5", 0xfffe3824, 16, 4) {
1493 { PINMUX_CFG_REG("PBCR4", 0xfffe3826, 16, 4) {
1503 { PINMUX_CFG_REG("PBCR3", 0xfffe3828, 16, 4) {
1513 { PINMUX_CFG_REG("PBCR2", 0xfffe382a, 16, 4) {
1523 { PINMUX_CFG_REG("PBCR1", 0xfffe382c, 16, 4) {
1533 { PINMUX_CFG_REG("PBCR0", 0xfffe382e, 16, 4) {
1544 { PINMUX_CFG_REG("PBIOR1", 0xfffe3830, 16, 1) {
1557 { PINMUX_CFG_REG("PBIOR0", 0xfffe3832, 16, 1) {
1576 { PINMUX_CFG_REG("PCCR2", 0xfffe384a, 16, 4) {
[all …]
Dpfc-sh7203.c1079 { PINMUX_CFG_REG("PBIORL", 0xfffe3886, 16, 1) {
1097 { PINMUX_CFG_REG("PBCRL4", 0xfffe3890, 16, 4) {
1107 { PINMUX_CFG_REG("PBCRL3", 0xfffe3892, 16, 4) {
1120 { PINMUX_CFG_REG("PBCRL2", 0xfffe3894, 16, 4) {
1133 { PINMUX_CFG_REG("PBCRL1", 0xfffe3896, 16, 4) {
1146 { PINMUX_CFG_REG("IFCR", 0xfffe38a2, 16, 4) {
1156 { PINMUX_CFG_REG("PCIORL", 0xfffe3906, 16, 1) {
1174 { PINMUX_CFG_REG("PCCRL4", 0xfffe3910, 16, 4) {
1186 { PINMUX_CFG_REG("PCCRL3", 0xfffe3912, 16, 4) {
1199 { PINMUX_CFG_REG("PCCRL2", 0xfffe3914, 16, 4) {
[all …]
Dpfc-sh7269.c1957 { PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1) {
1963 { PINMUX_CFG_REG("PBCR5", 0xfffe3824, 16, 4) {
1977 { PINMUX_CFG_REG("PBCR4", 0xfffe3826, 16, 4) {
1994 { PINMUX_CFG_REG("PBCR3", 0xfffe3828, 16, 4) {
2010 { PINMUX_CFG_REG("PBCR2", 0xfffe382a, 16, 4) {
2023 { PINMUX_CFG_REG("PBCR1", 0xfffe382c, 16, 4) {
2036 { PINMUX_CFG_REG("PBCR0", 0xfffe382e, 16, 4) {
2049 { PINMUX_CFG_REG("PBIOR1", 0xfffe3830, 16, 1) {
2061 { PINMUX_CFG_REG("PBIOR0", 0xfffe3832, 16, 1) {
2080 { PINMUX_CFG_REG("PCCR2", 0xfffe384a, 16, 4) {
[all …]
Dpfc-sh7722.c1239 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
1249 { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) {
1259 { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) {
1269 { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) {
1279 { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) {
1289 { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) {
1299 { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) {
1309 { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) {
1319 { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) {
1329 { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) {
[all …]
Dpfc-sh7757.c1690 { PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2) {
1700 { PINMUX_CFG_REG("PBCR", 0xffec0002, 16, 2) {
1710 { PINMUX_CFG_REG("PCCR", 0xffec0004, 16, 2) {
1720 { PINMUX_CFG_REG("PDCR", 0xffec0006, 16, 2) {
1730 { PINMUX_CFG_REG("PECR", 0xffec0008, 16, 2) {
1740 { PINMUX_CFG_REG("PFCR", 0xffec000a, 16, 2) {
1750 { PINMUX_CFG_REG("PGCR", 0xffec000c, 16, 2) {
1760 { PINMUX_CFG_REG("PHCR", 0xffec000e, 16, 2) {
1770 { PINMUX_CFG_REG("PICR", 0xffec0010, 16, 2) {
1780 { PINMUX_CFG_REG("PJCR", 0xffec0012, 16, 2) {
[all …]
Dpfc-sh7720.c931 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
941 { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) {
951 { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) {
961 { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) {
971 { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) {
981 { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) {
991 { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) {
1001 { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) {
1011 { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) {
1021 { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) {
[all …]
Dpfc-sh7785.c991 { PINMUX_CFG_REG("PACR", 0xffe70000, 16, 2) {
1001 { PINMUX_CFG_REG("PBCR", 0xffe70002, 16, 2) {
1011 { PINMUX_CFG_REG("PCCR", 0xffe70004, 16, 2) {
1021 { PINMUX_CFG_REG("PDCR", 0xffe70006, 16, 2) {
1031 { PINMUX_CFG_REG("PECR", 0xffe70008, 16, 2) {
1041 { PINMUX_CFG_REG("PFCR", 0xffe7000a, 16, 2) {
1051 { PINMUX_CFG_REG("PGCR", 0xffe7000c, 16, 2) {
1061 { PINMUX_CFG_REG("PHCR", 0xffe7000e, 16, 2) {
1071 { PINMUX_CFG_REG("PJCR", 0xffe70010, 16, 2) {
1081 { PINMUX_CFG_REG("PKCR", 0xffe70012, 16, 2) {
[all …]
Dpfc-sh7723.c1513 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
1523 { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) {
1533 { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) {
1543 { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) {
1553 { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) {
1563 { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) {
1573 { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) {
1583 { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) {
1593 { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) {
1603 { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) {
[all …]
Dpfc-sh7724.c1745 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
1755 { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) {
1765 { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) {
1775 { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) {
1785 { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) {
1795 { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) {
1805 { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) {
1815 { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) {
1825 { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) {
1835 { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) {
[all …]
Dpfc-sh7786.c633 { PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2) {
643 { PINMUX_CFG_REG("PBCR", 0xffcc0002, 16, 2) {
653 { PINMUX_CFG_REG("PCCR", 0xffcc0004, 16, 2) {
663 { PINMUX_CFG_REG("PDCR", 0xffcc0006, 16, 2) {
673 { PINMUX_CFG_REG("PECR", 0xffcc0008, 16, 2) {
683 { PINMUX_CFG_REG("PFCR", 0xffcc000a, 16, 2) {
693 { PINMUX_CFG_REG("PGCR", 0xffcc000c, 16, 2) {
703 { PINMUX_CFG_REG("PHCR", 0xffcc000e, 16, 2) {
713 { PINMUX_CFG_REG("PJCR", 0xffcc0010, 16, 2) {
723 { PINMUX_CFG_REG("P1MSELR", 0xffcc0080, 16, 1) {
[all …]
Dpfc-r8a7795.c2249 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
2283 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
2317 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
2351 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
2385 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
2419 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
2453 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
2487 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
2526 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
2536 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
[all …]
Dpfc-shx3.c437 { PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2) {
455 { PINMUX_CFG_REG("PCDCR", 0xffc70004, 32, 2) {
473 { PINMUX_CFG_REG("PEFCR", 0xffc70008, 32, 2) {
491 { PINMUX_CFG_REG("PGHCR", 0xffc7000c, 32, 2) {
Dpfc-sh7734.c1646 { PINMUX_CFG_REG("GPSR0", 0xFFFC0004, 32, 1) {
1680 { PINMUX_CFG_REG("GPSR1", 0xFFFC0008, 32, 1) {
1714 { PINMUX_CFG_REG("GPSR2", 0xFFFC000C, 32, 1) {
1748 { PINMUX_CFG_REG("GPSR3", 0xFFFC0010, 32, 1) {
1783 { PINMUX_CFG_REG("GPSR4", 0xFFFC0014, 32, 1) {
1817 { PINMUX_CFG_REG("GPSR5", 0xFFFC0018, 32, 1) {
2389 { PINMUX_CFG_REG("INOUTSEL0", 0xFFC40004, 32, 1) { GP_INOUTSEL(0) } },
2390 { PINMUX_CFG_REG("INOUTSEL1", 0xFFC41004, 32, 1) { GP_INOUTSEL(1) } },
2391 { PINMUX_CFG_REG("INOUTSEL2", 0xFFC42004, 32, 1) { GP_INOUTSEL(2) } },
2392 { PINMUX_CFG_REG("INOUTSEL3", 0xFFC43004, 32, 1) { GP_INOUTSEL(3) } },
[all …]
Dpfc-emev2.c1419 { PINMUX_CFG_REG("GPSR0", 0xe0140200, 32, 1) {
1454 { PINMUX_CFG_REG("GPSR1", 0xe0140204, 32, 1) {
1489 { PINMUX_CFG_REG("GPSR2", 0xe0140208, 32, 1) {
1524 { PINMUX_CFG_REG("GPSR3", 0xe014020c, 32, 1) {
1559 { PINMUX_CFG_REG("GPSR4", 0xe0140210, 32, 1) {
Dpfc-r8a73a4.c2301 { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
2336 { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
2371 { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
2406 { PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1) {
2441 { PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1) {
Dsh_pfc.h103 #define PINMUX_CFG_REG(name, r, r_width, f_width) \ macro
Dpfc-r8a7779.c3017 { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
3051 { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) {
3085 { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) {
3119 { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) {
3153 { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) {
3187 { PINMUX_CFG_REG("GPSR5", 0xfffc0018, 32, 1) {
3221 { PINMUX_CFG_REG("GPSR6", 0xfffc001c, 32, 1) {
Dpfc-r8a7791.c5141 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
5175 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
5209 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
5243 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
5277 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
5311 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
5345 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
5379 { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
Dpfc-r8a7794.c3454 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
3488 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
3522 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
3556 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
3590 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
3624 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
3658 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
Dpfc-r8a7778.c2114 { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
2148 { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) {
2182 { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) {
2216 { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) {
2250 { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) {
Dpfc-r8a7740.c3452 { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
3479 { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
3492 { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
3511 { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) {
Dpfc-r8a7790.c4748 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
4782 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
4816 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
4850 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
4884 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
4918 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
Dpfc-sh73a0.c3439 { PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1) {
3474 { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
3509 { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {