Searched refs:PCI_BASE_ADDRESS_IO_MASK (Results 1 – 11 of 11) sorted by relevance
335 pci_ioaddr1 &= PCI_BASE_ADDRESS_IO_MASK; in setup_sct_quadro()357 pci_ioaddr1 &= PCI_BASE_ADDRESS_IO_MASK; in setup_sct_quadro()358 pci_ioaddr2 &= PCI_BASE_ADDRESS_IO_MASK; in setup_sct_quadro()359 pci_ioaddr3 &= PCI_BASE_ADDRESS_IO_MASK; in setup_sct_quadro()360 pci_ioaddr4 &= PCI_BASE_ADDRESS_IO_MASK; in setup_sct_quadro()361 pci_ioaddr5 &= PCI_BASE_ADDRESS_IO_MASK; in setup_sct_quadro()
1676 … ((card->para[0]) && (card->para[0] != (tmp_hfcpci->resource[0].start & PCI_BASE_ADDRESS_IO_MASK))) in setup_hfcpci()
98 bar_size &= PCI_BASE_ADDRESS_IO_MASK; in pciauto_setup_bars()
345 smbus->base = iobase & PCI_BASE_ADDRESS_IO_MASK; in nforce2_probe_smb()
66 mask = (u32)PCI_BASE_ADDRESS_IO_MASK; in pci_update_resource()
136 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; in decode_bar()220 l64 = l & PCI_BASE_ADDRESS_IO_MASK; in __pci_read_base()221 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK; in __pci_read_base()222 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT; in __pci_read_base()
339 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; in quirk_io()
100 #define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) macro
241 ret &= PCI_BASE_ADDRESS_IO_MASK; in divasa_get_pci_bar()
1266 start_address &= PCI_BASE_ADDRESS_IO_MASK; in unconfigure_boot_device()1396 start_address &= PCI_BASE_ADDRESS_IO_MASK; in unconfigure_boot_bridge()
4791 io_port_base = pci_resource_start(dev, 0) & PCI_BASE_ADDRESS_IO_MASK; in dc395x_init_one()