Searched refs:PCIO (Results 1 - 11 of 11) sorted by relevance

/linux-4.4.14/drivers/video/fbdev/riva/
H A Drivafb-i2c.c33 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1); riva_gpio_setscl()
34 val = VGA_RD08(par->riva.PCIO, 0x3d5) & 0xf0; riva_gpio_setscl()
41 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1); riva_gpio_setscl()
42 VGA_WR08(par->riva.PCIO, 0x3d5, val | 0x1); riva_gpio_setscl()
51 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1); riva_gpio_setsda()
52 val = VGA_RD08(par->riva.PCIO, 0x3d5) & 0xf0; riva_gpio_setsda()
59 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1); riva_gpio_setsda()
60 VGA_WR08(par->riva.PCIO, 0x3d5, val | 0x1); riva_gpio_setsda()
69 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base); riva_gpio_getscl()
70 if (VGA_RD08(par->riva.PCIO, 0x3d5) & 0x04) riva_gpio_getscl()
82 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base); riva_gpio_getsda()
83 if (VGA_RD08(par->riva.PCIO, 0x3d5) & 0x08) riva_gpio_getsda()
H A Driva_hw.c92 VGA_WR08(chip->PCIO, 0x3D4, 0x11); vgaLockUnlock()
93 cr11 = VGA_RD08(chip->PCIO, 0x3D5); vgaLockUnlock()
96 VGA_WR08(chip->PCIO, 0x3D5, cr11); vgaLockUnlock()
114 VGA_WR08(chip->PCIO, 0x3D4, 0x1F); nv4LockUnlock()
115 VGA_WR08(chip->PCIO, 0x3D5, Lock ? 0x99 : 0x57); nv4LockUnlock()
129 VGA_WR08(chip->PCIO, 0x3D4, 0x31); ShowHideCursor()
130 VGA_WR08(chip->PCIO, 0x3D5, chip->CurrentState->cursor1); ShowHideCursor()
1505 VGA_WR08(chip->PCIO, 0x03D4, 0x44); LoadStateExt()
1506 VGA_WR08(chip->PCIO, 0x03D5, state->crtcOwner); LoadStateExt()
1670 VGA_WR08(chip->PCIO, 0x03D4, 0x53); LoadStateExt()
1671 VGA_WR08(chip->PCIO, 0x03D5, 0); LoadStateExt()
1672 VGA_WR08(chip->PCIO, 0x03D4, 0x54); LoadStateExt()
1673 VGA_WR08(chip->PCIO, 0x03D5, 0); LoadStateExt()
1674 VGA_WR08(chip->PCIO, 0x03D4, 0x21); LoadStateExt()
1675 VGA_WR08(chip->PCIO, 0x03D5, 0xfa); LoadStateExt()
1678 VGA_WR08(chip->PCIO, 0x03D4, 0x41); LoadStateExt()
1679 VGA_WR08(chip->PCIO, 0x03D5, state->extra); LoadStateExt()
1686 VGA_WR08(chip->PCIO, 0x03D4, 0x19); LoadStateExt()
1687 VGA_WR08(chip->PCIO, 0x03D5, state->repaint0); LoadStateExt()
1688 VGA_WR08(chip->PCIO, 0x03D4, 0x1A); LoadStateExt()
1689 VGA_WR08(chip->PCIO, 0x03D5, state->repaint1); LoadStateExt()
1690 VGA_WR08(chip->PCIO, 0x03D4, 0x25); LoadStateExt()
1691 VGA_WR08(chip->PCIO, 0x03D5, state->screen); LoadStateExt()
1692 VGA_WR08(chip->PCIO, 0x03D4, 0x28); LoadStateExt()
1693 VGA_WR08(chip->PCIO, 0x03D5, state->pixel); LoadStateExt()
1694 VGA_WR08(chip->PCIO, 0x03D4, 0x2D); LoadStateExt()
1695 VGA_WR08(chip->PCIO, 0x03D5, state->horiz); LoadStateExt()
1696 VGA_WR08(chip->PCIO, 0x03D4, 0x1B); LoadStateExt()
1697 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration0); LoadStateExt()
1698 VGA_WR08(chip->PCIO, 0x03D4, 0x20); LoadStateExt()
1699 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration1); LoadStateExt()
1700 VGA_WR08(chip->PCIO, 0x03D4, 0x30); LoadStateExt()
1701 VGA_WR08(chip->PCIO, 0x03D5, state->cursor0); LoadStateExt()
1702 VGA_WR08(chip->PCIO, 0x03D4, 0x31); LoadStateExt()
1703 VGA_WR08(chip->PCIO, 0x03D5, state->cursor1); LoadStateExt()
1704 VGA_WR08(chip->PCIO, 0x03D4, 0x2F); LoadStateExt()
1705 VGA_WR08(chip->PCIO, 0x03D5, state->cursor2); LoadStateExt()
1706 VGA_WR08(chip->PCIO, 0x03D4, 0x39); LoadStateExt()
1707 VGA_WR08(chip->PCIO, 0x03D5, state->interlace); LoadStateExt()
1748 VGA_WR08(chip->PCIO, 0x03D4, 0x19); UnloadStateExt()
1749 state->repaint0 = VGA_RD08(chip->PCIO, 0x03D5); UnloadStateExt()
1750 VGA_WR08(chip->PCIO, 0x03D4, 0x1A); UnloadStateExt()
1751 state->repaint1 = VGA_RD08(chip->PCIO, 0x03D5); UnloadStateExt()
1752 VGA_WR08(chip->PCIO, 0x03D4, 0x25); UnloadStateExt()
1753 state->screen = VGA_RD08(chip->PCIO, 0x03D5); UnloadStateExt()
1754 VGA_WR08(chip->PCIO, 0x03D4, 0x28); UnloadStateExt()
1755 state->pixel = VGA_RD08(chip->PCIO, 0x03D5); UnloadStateExt()
1756 VGA_WR08(chip->PCIO, 0x03D4, 0x2D); UnloadStateExt()
1757 state->horiz = VGA_RD08(chip->PCIO, 0x03D5); UnloadStateExt()
1758 VGA_WR08(chip->PCIO, 0x03D4, 0x1B); UnloadStateExt()
1759 state->arbitration0 = VGA_RD08(chip->PCIO, 0x03D5); UnloadStateExt()
1760 VGA_WR08(chip->PCIO, 0x03D4, 0x20); UnloadStateExt()
1761 state->arbitration1 = VGA_RD08(chip->PCIO, 0x03D5); UnloadStateExt()
1762 VGA_WR08(chip->PCIO, 0x03D4, 0x30); UnloadStateExt()
1763 state->cursor0 = VGA_RD08(chip->PCIO, 0x03D5); UnloadStateExt()
1764 VGA_WR08(chip->PCIO, 0x03D4, 0x31); UnloadStateExt()
1765 state->cursor1 = VGA_RD08(chip->PCIO, 0x03D5); UnloadStateExt()
1766 VGA_WR08(chip->PCIO, 0x03D4, 0x2F); UnloadStateExt()
1767 state->cursor2 = VGA_RD08(chip->PCIO, 0x03D5); UnloadStateExt()
1768 VGA_WR08(chip->PCIO, 0x03D4, 0x39); UnloadStateExt()
1769 state->interlace = VGA_RD08(chip->PCIO, 0x03D5); UnloadStateExt()
1812 VGA_WR08(chip->PCIO, 0x03D4, 0x44); UnloadStateExt()
1813 state->crtcOwner = VGA_RD08(chip->PCIO, 0x03D5); UnloadStateExt()
1815 VGA_WR08(chip->PCIO, 0x03D4, 0x41); UnloadStateExt()
1816 state->extra = VGA_RD08(chip->PCIO, 0x03D5); UnloadStateExt()
1854 VGA_WR08(chip->PCIO, 0x3D4, 0x0D); VGA_WR08(chip->PCIO, 0x3D5, offset); SetStartAddress3()
1856 VGA_WR08(chip->PCIO, 0x3D4, 0x0C); VGA_WR08(chip->PCIO, 0x3D5, offset); SetStartAddress3()
1858 VGA_WR08(chip->PCIO, 0x3D4, 0x19); tmp = VGA_RD08(chip->PCIO, 0x3D5); SetStartAddress3()
1859 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x01F) | (tmp & ~0x1F)); SetStartAddress3()
1860 VGA_WR08(chip->PCIO, 0x3D4, 0x2D); tmp = VGA_RD08(chip->PCIO, 0x3D5); SetStartAddress3()
1861 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x60) | (tmp & ~0x60)); SetStartAddress3()
1865 offset = VGA_RD08(chip->PCIO, chip->IO + 0x0A); SetStartAddress3()
1866 VGA_WR08(chip->PCIO, 0x3C0, 0x13); SetStartAddress3()
1867 VGA_WR08(chip->PCIO, 0x3C0, pan); SetStartAddress3()
H A Dnv_driver.c403 par->riva.PCIO = par->riva.PCIO0 + 0x2000; riva_common_setup()
408 par->riva.PCIO = par->riva.PCIO0; riva_common_setup()
H A Dfbdev.c391 VGA_WR08(par->riva.PCIO, 0x3d4, index); CRTCout()
392 VGA_WR08(par->riva.PCIO, 0x3d5, val); CRTCout()
398 VGA_WR08(par->riva.PCIO, 0x3d4, index); CRTCin()
399 return (VGA_RD08(par->riva.PCIO, 0x3d5)); CRTCin()
433 VGA_WR08(par->riva.PCIO, 0x3c0, index); ATTRout()
434 VGA_WR08(par->riva.PCIO, 0x3c0, val); ATTRout()
440 VGA_WR08(par->riva.PCIO, 0x3c0, index); ATTRin()
441 return (VGA_RD08(par->riva.PCIO, 0x3c1)); ATTRin()
H A Driva_hw.h457 volatile U008 __iomem *PCIO; member in struct:_riva_hw_inst
/linux-4.4.14/drivers/video/fbdev/nvidia/
H A Dnv_hw.c61 VGA_WR08(par->PCIO, 0x3D4, 0x1F); NVLockUnlock()
62 VGA_WR08(par->PCIO, 0x3D5, Lock ? 0x99 : 0x57); NVLockUnlock()
64 VGA_WR08(par->PCIO, 0x3D4, 0x11); NVLockUnlock()
65 cr11 = VGA_RD08(par->PCIO, 0x3D5); NVLockUnlock()
70 VGA_WR08(par->PCIO, 0x3D5, cr11); NVLockUnlock()
79 VGA_WR08(par->PCIO, 0x3D4, 0x31); NVShowHideCursor()
80 VGA_WR08(par->PCIO, 0x3D5, par->CurrentState->cursor1); NVShowHideCursor()
1543 VGA_WR08(par->PCIO, 0x03D4, 0x53); NVLoadStateExt()
1544 VGA_WR08(par->PCIO, 0x03D5, state->timingH); NVLoadStateExt()
1545 VGA_WR08(par->PCIO, 0x03D4, 0x54); NVLoadStateExt()
1546 VGA_WR08(par->PCIO, 0x03D5, state->timingV); NVLoadStateExt()
1547 VGA_WR08(par->PCIO, 0x03D4, 0x21); NVLoadStateExt()
1548 VGA_WR08(par->PCIO, 0x03D5, 0xfa); NVLoadStateExt()
1551 VGA_WR08(par->PCIO, 0x03D4, 0x41); NVLoadStateExt()
1552 VGA_WR08(par->PCIO, 0x03D5, state->extra); NVLoadStateExt()
1555 VGA_WR08(par->PCIO, 0x03D4, 0x19); NVLoadStateExt()
1556 VGA_WR08(par->PCIO, 0x03D5, state->repaint0); NVLoadStateExt()
1557 VGA_WR08(par->PCIO, 0x03D4, 0x1A); NVLoadStateExt()
1558 VGA_WR08(par->PCIO, 0x03D5, state->repaint1); NVLoadStateExt()
1559 VGA_WR08(par->PCIO, 0x03D4, 0x25); NVLoadStateExt()
1560 VGA_WR08(par->PCIO, 0x03D5, state->screen); NVLoadStateExt()
1561 VGA_WR08(par->PCIO, 0x03D4, 0x28); NVLoadStateExt()
1562 VGA_WR08(par->PCIO, 0x03D5, state->pixel); NVLoadStateExt()
1563 VGA_WR08(par->PCIO, 0x03D4, 0x2D); NVLoadStateExt()
1564 VGA_WR08(par->PCIO, 0x03D5, state->horiz); NVLoadStateExt()
1565 VGA_WR08(par->PCIO, 0x03D4, 0x1C); NVLoadStateExt()
1566 VGA_WR08(par->PCIO, 0x03D5, state->fifo); NVLoadStateExt()
1567 VGA_WR08(par->PCIO, 0x03D4, 0x1B); NVLoadStateExt()
1568 VGA_WR08(par->PCIO, 0x03D5, state->arbitration0); NVLoadStateExt()
1569 VGA_WR08(par->PCIO, 0x03D4, 0x20); NVLoadStateExt()
1570 VGA_WR08(par->PCIO, 0x03D5, state->arbitration1); NVLoadStateExt()
1573 VGA_WR08(par->PCIO, 0x03D4, 0x47); NVLoadStateExt()
1574 VGA_WR08(par->PCIO, 0x03D5, state->arbitration1 >> 8); NVLoadStateExt()
1577 VGA_WR08(par->PCIO, 0x03D4, 0x30); NVLoadStateExt()
1578 VGA_WR08(par->PCIO, 0x03D5, state->cursor0); NVLoadStateExt()
1579 VGA_WR08(par->PCIO, 0x03D4, 0x31); NVLoadStateExt()
1580 VGA_WR08(par->PCIO, 0x03D5, state->cursor1); NVLoadStateExt()
1581 VGA_WR08(par->PCIO, 0x03D4, 0x2F); NVLoadStateExt()
1582 VGA_WR08(par->PCIO, 0x03D5, state->cursor2); NVLoadStateExt()
1583 VGA_WR08(par->PCIO, 0x03D4, 0x39); NVLoadStateExt()
1584 VGA_WR08(par->PCIO, 0x03D5, state->interlace); NVLoadStateExt()
1613 VGA_WR08(par->PCIO, 0x03D4, 0x19); NVUnloadStateExt()
1614 state->repaint0 = VGA_RD08(par->PCIO, 0x03D5); NVUnloadStateExt()
1615 VGA_WR08(par->PCIO, 0x03D4, 0x1A); NVUnloadStateExt()
1616 state->repaint1 = VGA_RD08(par->PCIO, 0x03D5); NVUnloadStateExt()
1617 VGA_WR08(par->PCIO, 0x03D4, 0x25); NVUnloadStateExt()
1618 state->screen = VGA_RD08(par->PCIO, 0x03D5); NVUnloadStateExt()
1619 VGA_WR08(par->PCIO, 0x03D4, 0x28); NVUnloadStateExt()
1620 state->pixel = VGA_RD08(par->PCIO, 0x03D5); NVUnloadStateExt()
1621 VGA_WR08(par->PCIO, 0x03D4, 0x2D); NVUnloadStateExt()
1622 state->horiz = VGA_RD08(par->PCIO, 0x03D5); NVUnloadStateExt()
1623 VGA_WR08(par->PCIO, 0x03D4, 0x1C); NVUnloadStateExt()
1624 state->fifo = VGA_RD08(par->PCIO, 0x03D5); NVUnloadStateExt()
1625 VGA_WR08(par->PCIO, 0x03D4, 0x1B); NVUnloadStateExt()
1626 state->arbitration0 = VGA_RD08(par->PCIO, 0x03D5); NVUnloadStateExt()
1627 VGA_WR08(par->PCIO, 0x03D4, 0x20); NVUnloadStateExt()
1628 state->arbitration1 = VGA_RD08(par->PCIO, 0x03D5); NVUnloadStateExt()
1631 VGA_WR08(par->PCIO, 0x03D4, 0x47); NVUnloadStateExt()
1632 state->arbitration1 |= (VGA_RD08(par->PCIO, 0x03D5) & 1) << 8; NVUnloadStateExt()
1635 VGA_WR08(par->PCIO, 0x03D4, 0x30); NVUnloadStateExt()
1636 state->cursor0 = VGA_RD08(par->PCIO, 0x03D5); NVUnloadStateExt()
1637 VGA_WR08(par->PCIO, 0x03D4, 0x31); NVUnloadStateExt()
1638 state->cursor1 = VGA_RD08(par->PCIO, 0x03D5); NVUnloadStateExt()
1639 VGA_WR08(par->PCIO, 0x03D4, 0x2F); NVUnloadStateExt()
1640 state->cursor2 = VGA_RD08(par->PCIO, 0x03D5); NVUnloadStateExt()
1641 VGA_WR08(par->PCIO, 0x03D4, 0x39); NVUnloadStateExt()
1642 state->interlace = VGA_RD08(par->PCIO, 0x03D5); NVUnloadStateExt()
1662 VGA_WR08(par->PCIO, 0x03D4, 0x44); NVUnloadStateExt()
1663 state->crtcOwner = VGA_RD08(par->PCIO, 0x03D5); NVUnloadStateExt()
1665 VGA_WR08(par->PCIO, 0x03D4, 0x41); NVUnloadStateExt()
1666 state->extra = VGA_RD08(par->PCIO, 0x03D5); NVUnloadStateExt()
1676 VGA_WR08(par->PCIO, 0x03D4, 0x53); NVUnloadStateExt()
1677 state->timingH = VGA_RD08(par->PCIO, 0x03D5); NVUnloadStateExt()
1678 VGA_WR08(par->PCIO, 0x03D4, 0x54); NVUnloadStateExt()
1679 state->timingV = VGA_RD08(par->PCIO, 0x03D5); NVUnloadStateExt()
H A Dnv_setup.c62 VGA_WR08(par->PCIO, par->IOBase + 0x04, index); NVWriteCrtc()
63 VGA_WR08(par->PCIO, par->IOBase + 0x05, value); NVWriteCrtc()
67 VGA_WR08(par->PCIO, par->IOBase + 0x04, index); NVReadCrtc()
68 return (VGA_RD08(par->PCIO, par->IOBase + 0x05)); NVReadCrtc()
94 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a); NVWriteAttr()
99 VGA_WR08(par->PCIO, VGA_ATT_IW, index); NVWriteAttr()
100 VGA_WR08(par->PCIO, VGA_ATT_W, value); NVWriteAttr()
106 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a); NVReadAttr()
111 VGA_WR08(par->PCIO, VGA_ATT_IW, index); NVReadAttr()
112 return (VGA_RD08(par->PCIO, VGA_ATT_R)); NVReadAttr()
127 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
128 VGA_WR08(par->PCIO, VGA_ATT_IW, 0x00);
135 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
136 VGA_WR08(par->PCIO, VGA_ATT_IW, 0x20);
212 par->PCIO = par->PCIO0 + 0x2000; NVSelectHeadRegisters()
217 par->PCIO = par->PCIO0; NVSelectHeadRegisters()
437 VGA_WR08(par->PCIO, 0x03D4, 0x28); NVCommonSetup()
438 if (VGA_RD08(par->PCIO, 0x03D5) & 0x80) { NVCommonSetup()
439 VGA_WR08(par->PCIO, 0x03D4, 0x33); NVCommonSetup()
440 if (!(VGA_RD08(par->PCIO, 0x03D5) & 0x01)) NVCommonSetup()
484 VGA_WR08(par->PCIO, 0x03D4, 0x44); NVCommonSetup()
485 cr44 = VGA_RD08(par->PCIO, 0x03D5); NVCommonSetup()
487 VGA_WR08(par->PCIO, 0x03D5, 3); NVCommonSetup()
491 VGA_WR08(par->PCIO, 0x03D4, 0x28); NVCommonSetup()
492 slaved_on_B = VGA_RD08(par->PCIO, 0x03D5) & 0x80; NVCommonSetup()
494 VGA_WR08(par->PCIO, 0x03D4, 0x33); NVCommonSetup()
495 tvB = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01); NVCommonSetup()
498 VGA_WR08(par->PCIO, 0x03D4, 0x44); NVCommonSetup()
499 VGA_WR08(par->PCIO, 0x03D5, 0); NVCommonSetup()
503 VGA_WR08(par->PCIO, 0x03D4, 0x28); NVCommonSetup()
504 slaved_on_A = VGA_RD08(par->PCIO, 0x03D5) & 0x80; NVCommonSetup()
506 VGA_WR08(par->PCIO, 0x03D4, 0x33); NVCommonSetup()
507 tvA = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01); NVCommonSetup()
637 VGA_WR08(par->PCIO, 0x03D4, 0x44); NVCommonSetup()
638 VGA_WR08(par->PCIO, 0x03D5, cr44); NVCommonSetup()
H A Dnv_type.h168 volatile u8 __iomem *PCIO; member in struct:nvidia_par
H A Dnvidia.c440 VGA_WR08(par->PCIO, 0x03D4, 0x1C); nvidia_calc_regs()
441 state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5); nvidia_calc_regs()
638 VGA_WR08(par->PCIO, 0x03D4, 0x44); nvidiafb_set_par()
639 VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner); nvidiafb_set_par()
653 VGA_WR08(par->PCIO, 0x3d4, 0x46); nvidiafb_set_par()
654 tmp = VGA_RD08(par->PCIO, 0x3d5); nvidiafb_set_par()
656 VGA_WR08(par->PCIO, 0x3d5, tmp); nvidiafb_set_par()
/linux-4.4.14/arch/sparc/include/asm/
H A Dauxio_64.h6 * Refactoring for unified NCR/PCIO support 2002 Eric Brower (ebrower@usa.net)
16 * ebus-based auxio on PCIO
56 * PCIO LED Auxio @ 0x726000
65 /* PCIO Power Auxio @ 0x724000
/linux-4.4.14/arch/sparc/kernel/
H A Dauxio_64.c5 * Refactoring for unified NCR/PCIO support 2002 Eric Brower (ebrower@usa.net)

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