Searched refs:PACKET3_PREAMBLE_END_CLEAR_STATE (Results 1 – 12 of 12) sorted by relevance
269 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
384 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
2904 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v7_0_cp_gfx_start()4631 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v7_0_get_csb_buffer()
3280 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v8_0_cp_gfx_start()
1262 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
1775 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
1857 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
1656 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
1591 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in cayman_cp_start()
3600 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in si_cp_start()5756 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in si_get_csb_buffer()
4422 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in cik_cp_gfx_start()7203 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in cik_get_csb_buffer()
3123 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in evergreen_cp_start()