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Searched refs:OMAP1_IO_ADDRESS (Results 1 – 8 of 8) sorted by relevance

/linux-4.4.14/arch/arm/mach-omap1/
Dclock_data.c101 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
113 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
135 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
154 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
165 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
178 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
191 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
215 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
301 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
310 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
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Dsram.S28 mov r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0xff000000
29 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000
30 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00
32 mov r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0xff000000
33 orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x00ff0000
34 orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x0000ff00
Dio.c150 return __raw_readb(OMAP1_IO_ADDRESS(pa)); in omap_readb()
156 return __raw_readw(OMAP1_IO_ADDRESS(pa)); in omap_readw()
162 return __raw_readl(OMAP1_IO_ADDRESS(pa)); in omap_readl()
168 __raw_writeb(v, OMAP1_IO_ADDRESS(pa)); in omap_writeb()
174 __raw_writew(v, OMAP1_IO_ADDRESS(pa)); in omap_writew()
180 __raw_writel(v, OMAP1_IO_ADDRESS(pa)); in omap_writel()
Dpm.h42 #define CLKGEN_REG_ASM_BASE OMAP1_IO_ADDRESS(0xfffece00)
46 #define TCMIF_ASM_BASE OMAP1_IO_ADDRESS(0xfffecc00)
Dreset.c51 rs = __raw_readw(OMAP1_IO_ADDRESS(ARM_SYSST)); in omap1_get_reset_sources()
Dtime.c69 ((omap_mpu_timer_regs_t __iomem *)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \
/linux-4.4.14/arch/arm/mach-omap1/include/mach/
Dmtd-xip.h28 ((volatile xip_omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \
Dhardware.h76 #define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET) macro