Searched refs:Mode (Results 1 - 200 of 1392) sorted by relevance

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/linux-4.4.14/arch/arm/mach-ks8695/include/mach/
H A Dregs-gpio.h21 #define KS8695_IOPM (0x00) /* I/O Port Mode Register */
26 /* Port Mode Register */
27 #define IOPM(x) (1 << (x)) /* Mode for GPIO Pin x */
33 #define IOPC_IOEINT3TM (7 << 12) /* GPIO Pin for External/Soft Interrupt 3 Trigger Mode */
36 #define IOPC_IOEINT2TM (7 << 8) /* GPIO Pin for External/Soft Interrupt 2 Trigger Mode */
39 #define IOPC_IOEINT1TM (7 << 4) /* GPIO Pin for External/Soft Interrupt 1 Trigger Mode */
42 #define IOPC_IOEINT0TM (7 << 0) /* GPIO Pin for External/Soft Interrupt 0 Trigger Mode */
H A Dregs-sys.h30 #define CLKCON_SFMODE (1 << 8) /* System Fast Mode for Simulation */
H A Dregs-mem.h50 #define ROMCON_PMC (3 << 0) /* Page Mode Configuration */
83 #define SDBCON_SDMODE (0x3fff << 0) /* SDRAM Mode Register Value Program */
H A Dregs-irq.h25 #define KS8695_INTMC (0x00) /* Mode Control Register */
H A Dregs-pci.h28 #define KS8695_PBM (0x200) /* Bridge Mode */
/linux-4.4.14/arch/microblaze/include/asm/
H A Dregisters.h35 # define MSR_UM (1<<11) /* User Mode */
36 # define MSR_UMS (1<<12) /* User Mode Save */
37 # define MSR_VM (1<<13) /* Virtual Mode */
38 # define MSR_VMS (1<<14) /* Virtual Mode Save */
/linux-4.4.14/drivers/scsi/aic94xx/
H A Daic94xx_reg_def.h520 #define CSEQm_CIO_REG(Mode, Reg) \
522 ((u32) (Mode) * CSEQ_MODE_PAGE_SIZE) + (u32) (Reg))
570 #define CMnSCBPTR(Mode) CSEQm_CIO_REG(Mode, MnSCBPTR)
572 #define CMnDDBPTR(Mode) CSEQm_CIO_REG(Mode, MnDDBPTR)
574 #define CMnSCRATCHPAGE(Mode) CSEQm_CIO_REG(Mode, MnSCRATCHPAGE)
582 #define CMnREQMBX(Mode) CSEQm_CIO_REG(Mode, 0x30)
589 #define CMnRSPMBX(Mode) CSEQm_CIO_REG(Mode, 0x34)
611 #define CMnINT(Mode) CSEQm_CIO_REG(Mode, 0x38)
622 #define CMnINTEN(Mode) CSEQm_CIO_REG(Mode, 0x3C)
681 #define CMnSCRATCH(Mode) CSEQm_CIO_REG(Mode, 0x1E0)
850 #define LmSEQ_PHY_BASE(Mode, LinkNum) \
854 ((u32) (Mode) * LmSEQ_MODE_PAGE_SIZE))
856 #define LmSEQ_PHY_REG(Mode, LinkNum, Reg) \
857 (LmSEQ_PHY_BASE(Mode, LinkNum) + (u32) (Reg))
905 #define LmMnSCRATCHPAGE(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, \
914 #define LmMnINT(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x38)
944 #define LmMnINTEN(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x3C)
1004 #define LmMnDMAERRS(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x46)
1006 #define LmMnSGDMAERRS(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x47)
1037 #define LmMnBUFSTAT(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x4E)
1042 #define LmMnXFRLVL(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x59)
1052 #define LmMnSGDMACTL(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x5A)
1059 #define LmMnSGDMASTAT(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x5B)
1062 #define LmMnDDMACTL(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x5C)
1073 #define LmMnDDMASTAT(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x5D)
1085 #define LmMnDDMAMODE(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x5E)
1104 #define LmMnXFRCNT(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x70)
1107 #define LmMnDPSEL(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x7B)
1113 /* Receive Mode n = 0 */
1122 /* Transmit Mode n = 1 */
1131 #define LmMnDPACC(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x78)
1135 #define LmMnHOLDLVL(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x7D)
1210 #define LmMnSATAFS(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x7E)
1211 #define LmMnXMTSIZE(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x93)
1214 #define LmMnFRMERR(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0xB0)
1274 #define LmMnDATABUFADR(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0xC8)
1277 #define LmMnDATABUF(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0xCA)
1361 * LmSEQ CIO Bus Mode 3 Register.
1362 * Mode 3: Configuration and Setup, IOP Context SCB.
1396 * LmSEQ CIO Bus Mode 5 Registers.
1397 * Mode 5: Phy/OOB Control and Status.
1985 * Mode Independent memory (four 32 byte pages 3-7). Note that mode
1986 * dependent scratch memory, Mode 8, page 0-3 overlaps mode
1996 * dependent scratch memory for modes 0-7 (768 bytes). Mode 8 pages
2009 * 800h-83Fh Mode Dependent Scratch Mode 0 Pages 0-1
2010 * 840h-87Fh Mode Dependent Scratch Mode 1 Pages 0-1
2011 * 880h-8BFh Mode Dependent Scratch Mode 2 Pages 0-1
2012 * 8C0h-8FFh Mode Dependent Scratch Mode 3 Pages 0-1
2013 * 900h-93Fh Mode Dependent Scratch Mode 4 Pages 0-1
2014 * 940h-97Fh Mode Dependent Scratch Mode 5 Pages 0-1
2015 * 980h-9BFh Mode Dependent Scratch Mode 6 Pages 0-1
2016 * 9C0h-9FFh Mode Dependent Scratch Mode 7 Pages 0-1
2017 * A00h-A5Fh Mode Dependent Scratch Mode 8 Pages 0-2
2018 * Mode Independent Scratch Pages 0-2
2019 * A60h-A7Fh Mode Dependent Scratch Mode 8 Page 3
2020 * Mode Independent Scratch Page 3
2021 * A80h-AFFh Mode Independent Scratch Pages 4-7
2022 * B00h-B1Fh Mode Dependent Scratch Mode 0 Page 2
2023 * B20h-B3Fh Mode Dependent Scratch Mode 1 Page 2
2024 * B40h-B5Fh Mode Dependent Scratch Mode 2 Page 2
2025 * B60h-B7Fh Mode Dependent Scratch Mode 3 Page 2
2026 * B80h-B9Fh Mode Dependent Scratch Mode 4 Page 2
2027 * BA0h-BBFh Mode Dependent Scratch Mode 5 Page 2
2028 * BC0h-BDFh Mode Dependent Scratch Mode 6 Page 2
2029 * BE0h-BFFh Mode Dependent Scratch Mode 7 Page 2
2036 * Mode dependent scratch page 0, mode 0.
2044 /* Mode dependent scratch page 0 mode 8 macros. */
2060 /* Mode dependent scratch page 1 mode 8 macros. */
2064 /* Mode dependent scratch page 2 mode 8 macros */
2070 /* Mode independent scratch page 4 macros. */
2088 /* Mode independent scratch page 5 macros. */
2098 /* Mode independent scratch page 6 macros. */
2114 /* Mode independent scratch page 7 macros. */
2143 * 800h-85Fh Mode Dependent Scratch Mode 0 Pages 0-2
2144 * 860h-87Fh Mode Dependent Scratch Mode 0 Page 3
2145 * Mode Dependent Scratch Mode 5 Page 0
2146 * 880h-8DFh Mode Dependent Scratch Mode 1 Pages 0-2
2147 * 8E0h-8FFh Mode Dependent Scratch Mode 1 Page 3
2148 * Mode Dependent Scratch Mode 5 Page 1
2149 * 900h-95Fh Mode Dependent Scratch Mode 2 Pages 0-2
2150 * 960h-97Fh Mode Dependent Scratch Mode 2 Page 3
2151 * Mode Dependent Scratch Mode 5 Page 2
2152 * 980h-9DFh Mode Independent Scratch Pages 0-3
2153 * 9E0h-9FFh Mode Independent Scratch Page 3
2154 * Mode Dependent Scratch Mode 5 Page 3
2168 /* Mode flag macros (byte 0) */
2178 /* Mode flag macros (byte 1) */
2187 /* Mode dependent scratch page 0 macros for mode 0 (non-common) */
2200 /* Mode dependent scratch page 0 macros for mode 1 (non-common) */
2211 /* Mode dependent scratch page 0 macros for mode 2 (non-common) */
2219 /* Mode dependent scratch page 0 macros for modes 4/5 (non-common) */
2234 /* Mode dependent scratch page 1, mode 0 and mode 1 */
2240 /* Mode dependent scratch page 1 macros for mode 2 */
2246 /* Mode dependent scratch page 1 macros for mode 4/5 */
2256 /* Mode dependent scratch page 2 macros for mode 0 */
2264 /* Mode dependent scratch page 2 macros for mode 1 */
2272 /* Mode dependent scratch page 2 macros for mode 2 */
2282 /* Mode dependent scratch page 2 macros for mode 5 */
2288 /* Mode dependent scratch page 3 macros for modes 0 and 1 */
2291 /* Mode dependent scratch page 3 macros for modes 2 and 5 */
2294 /* Mode Independent Scratch page 0 macros. */
2359 /* Mode independent scratch page 1 macros. */
2375 /* Mode independent scratch page 2 macros. */
2389 /* Mode independent scratch page 3 macros. */
H A Daic94xx_seq.c448 /* CSEQ Mode Independent, page 4 setup. */ asd_init_cseq_mip()
470 /* CSEQ Mode independent, page 5 setup. */ asd_init_cseq_mip()
482 /* CSEQ Mode independent, page 6 setup. */ asd_init_cseq_mip()
505 /* CSEQ Mode independent, page 7 setup. */ asd_init_cseq_mip()
521 * asd_init_cseq_mdp - initialize CSEQ Mode dependent pages
531 /* CSEQ Mode dependent, modes 0-7, page 0 setup. */ asd_init_cseq_mdp()
540 /* CSEQ Mode dependent, mode 0-7, page 1 and 2 shall be ignored. */ asd_init_cseq_mdp()
542 /* CSEQ Mode dependent, mode 8, page 0 setup. */ asd_init_cseq_mdp()
560 /* CSEQ Mode dependent, mode 8, page 1 setup. */ asd_init_cseq_mdp()
566 /* CSEQ Mode dependent, mode 8, page 2 setup. */ asd_init_cseq_mdp()
584 /* CSEQ Mode dependent, mode 8, page 3 shall be ignored. */ asd_init_cseq_mdp()
601 * asd_init_lseq_mip -- initialize LSEQ Mode independent pages 0-3
608 /* LSEQ Mode independent page 0 setup. */ asd_init_lseq_mip()
624 /* LSEQ Mode independent page 1 setup. */ asd_init_lseq_mip()
640 /* LSEQ Mode Independent page 2 setup. */ asd_init_lseq_mip()
655 /* LSEQ Mode Independent page 3 setup. */ asd_init_lseq_mip()
705 * Mode 0,1,2 and 4/5 have common field on page 0 for the first asd_init_lseq_mdp()
720 * Mode 5 page 0 overlaps the same scratch page with Mode 0 page 3. asd_init_lseq_mdp()
738 /* LSEQ Mode dependent 0, page 0 setup. */ asd_init_lseq_mdp()
765 /* LSEQ Mode dependent mode 2, page 0 setup */ asd_init_lseq_mdp()
773 /* LSEQ Mode dependent, mode 4/5, page 0 setup. */ asd_init_lseq_mdp()
795 /* LSEQ Mode dependent, mode 0 and 1, page 1 setup. */ asd_init_lseq_mdp()
798 /* Start from Page 1 of Mode 0 and 1. */ asd_init_lseq_mdp()
805 /* LSEQ Mode dependent, mode 2, page 1 setup. */ asd_init_lseq_mdp()
810 /* LSEQ Mode dependent, mode 4/5, page 1. */ asd_init_lseq_mdp()
822 /* LSEQ Mode dependent, mode 0, page 2 setup. */ asd_init_lseq_mdp()
829 /* LSEQ Mode Dependent 1, page 2 setup. */ asd_init_lseq_mdp()
836 /* LSEQ Mode Dependent 2, page 2 setup. */ asd_init_lseq_mdp()
846 /* LSEQ Mode Dependent 4/5, page 2 setup. */ asd_init_lseq_mdp()
941 /* Initialize CSEQ Mode 11 Interrupt Vectors. asd_init_cseq_cio()
955 /* Initialize CSEQ Mode[0-8] Dependent registers. */ asd_init_cseq_cio()
964 /* Initialize Mode n Link m Interrupt Enable. */ asd_init_cseq_cio()
966 /* Initialize Mode n Request Mailbox. */ asd_init_cseq_cio()
985 /* Initialize Mode 0,1, and 2 SCRATCHPAGE to 0. */ asd_init_lseq_cio()
989 /* Initialize Mode 5 SCRATCHPAGE to 0. */ asd_init_lseq_cio()
993 /* Initialize Mode 0,1,2 and 5 Interrupt Enable and asd_init_lseq_cio()
997 /* Mode 1 */ asd_init_lseq_cio()
1000 /* Mode 2 */ asd_init_lseq_cio()
1003 /* Mode 5 */ asd_init_lseq_cio()
1018 /* Initialize Mode 0 Transfer Level to 512. */ asd_init_lseq_cio()
1020 /* Initialize Mode 1 Transfer Level to 256. */ asd_init_lseq_cio()
1040 /* Clear DMA Errors for Mode 0 and 1. */ asd_init_lseq_cio()
1044 /* Clear SG DMA Errors for Mode 0 and 1. */ asd_init_lseq_cio()
1048 /* Clear Mode 0 Buffer Parity Error. */ asd_init_lseq_cio()
1051 /* Clear Mode 0 Frame Error register. */ asd_init_lseq_cio()
1071 /* Initialize Interrupt Vector[0-10] address in Mode 3. asd_init_lseq_cio()
1098 * asd_post_init_cseq -- clear CSEQ Mode n Int. status and Response mailbox
/linux-4.4.14/drivers/mtd/nand/
H A Dnand_timings.c17 /* Mode 0 */
54 /* Mode 1 */
91 /* Mode 2 */
128 /* Mode 3 */
165 /* Mode 4 */
202 /* Mode 5 */
/linux-4.4.14/sound/soc/codecs/
H A Dlm4857.c64 SOC_DAPM_ENUM("Mode", lm4857_mode_enum);
69 SND_SOC_DAPM_DEMUX("Mode", SND_SOC_NOPM, 0, 0, &lm4857_mode_ctrl),
95 { "Mode", NULL, "IN" },
96 { "LS", "Loudspeaker", "Mode" },
97 { "LS", "Loudspeaker + Headphone", "Mode" },
98 { "HP", "Headphone", "Mode" },
99 { "HP", "Loudspeaker + Headphone", "Mode" },
100 { "EP", "Earpiece", "Mode" },
H A Dadau17x1.c58 SOC_ENUM("Mic Bias Mode", adau17x1_mic_bias_mode_enum),
103 SOC_DAPM_ENUM("DAC Mono-Stereo-Mode", adau17x1_dac_mode_enum);
118 SND_SOC_DAPM_MUX("Left DAC Mode Mux", SND_SOC_NOPM, 0, 0,
120 SND_SOC_DAPM_MUX("Right DAC Mode Mux", SND_SOC_NOPM, 0, 0,
137 { "Left DAC", NULL, "Left DAC Mode Mux" },
138 { "Right DAC", NULL, "Right DAC Mode Mux" },
262 { "Left DAC Mode Mux", "Stereo", "DAC Playback Mux" },
263 { "Left DAC Mode Mux", "Mono (L+R)", "DAC Playback Mux" },
264 { "Left DAC Mode Mux", "Mono Left Channel (L+R)", "DAC Playback Mux" },
265 { "Right DAC Mode Mux", "Stereo", "DAC Playback Mux" },
266 { "Right DAC Mode Mux", "Mono (L+R)", "DAC Playback Mux" },
267 { "Right DAC Mode Mux", "Mono Right Channel (L+R)", "DAC Playback Mux" },
282 { "Left DAC Mode Mux", "Stereo", "Playback" },
283 { "Left DAC Mode Mux", "Mono (L+R)", "Playback" },
284 { "Left DAC Mode Mux", "Mono Left Channel (L+R)", "Playback" },
285 { "Right DAC Mode Mux", "Stereo", "Playback" },
286 { "Right DAC Mode Mux", "Mono (L+R)", "Playback" },
287 { "Right DAC Mode Mux", "Mono Right Channel (L+R)", "Playback" },
H A Dmax9877.c84 SOC_SINGLE("MAX9877 Bypass Mode Switch",
86 SOC_ENUM("MAX9877 Output Mode", max9877_enum[0]),
87 SOC_ENUM("MAX9877 Oscillator Mode", max9877_enum[1]),
H A Dcs35l32.h58 #define CS35L32_FLASH_MODE 0x19 /* LED Flash Mode Current */
59 #define CS35L32_MOVIE_MODE 0x1A /* LED Movie Mode Current */
H A Dssm2602.h109 #define PWR_POWER_OFF 0x080 /* POWEROFF Mode */
116 #define IFACE_ENABLE_MASTER 0x040 /* Enable/Disable Master Mode */
120 #define SRATE_ENABLE_USB_MODE 0x001 /* Enable/Disable USB Mode */
H A Dcs4349.h24 #define CS4349_MODE 0x02 /* Mode Control */
51 /* (Digital Interface Format, De-Emphasis Control, Functional Mode */
H A Dwm8903.c648 SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
655 SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
661 SOC_ENUM("HPF Mode", hpf_mode),
684 SOC_ENUM("ADC Companding Mode", adc_companding),
695 SOC_ENUM("DAC Mute Mode", mute_mode),
697 SOC_ENUM("DAC Companding Mode", dac_companding),
737 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
740 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
829 SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
834 SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
955 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
956 { "Left Input Mode Mux", "Differential Line",
958 { "Left Input Mode Mux", "Differential Line",
960 { "Left Input Mode Mux", "Differential Mic",
962 { "Left Input Mode Mux", "Differential Mic",
965 { "Right Input Mode Mux", "Single-Ended",
967 { "Right Input Mode Mux", "Differential Line",
969 { "Right Input Mode Mux", "Differential Line",
971 { "Right Input Mode Mux", "Differential Mic",
973 { "Right Input Mode Mux", "Differential Mic",
976 { "Left Input PGA", NULL, "Left Input Mode Mux" },
977 { "Right Input PGA", NULL, "Right Input Mode Mux" },
/linux-4.4.14/arch/blackfin/include/asm/
H A Dbfin_dma.h30 #define DMA2D 0x04000000 /* DMA Mode (2D/1D*) */
45 #define DMAFLOW_LIST 0x00004000 /* Descriptor List Mode */
47 #define DMAFLOW_ARRAY 0x00005000 /* Descriptor Array Mode */
48 #define DMAFLOW_LIST_DEMAND 0x00006000 /* Descriptor Demand List Mode */
49 #define DMAFLOW_ARRAY_DEMAND 0x00007000 /* Descriptor Demand Array Mode */
61 #define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
79 #define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
80 #define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
81 #define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
87 #define DMAFLOW_STOP 0x0000 /* Stop Mode */
88 #define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
H A Dbfin_ppi.h107 #define EPPI_CTL_XFRTYPE 0x0000000C /* PPI Operating Mode */
108 #define EPPI_CTL_ACTIVE656 0x00000000 /* XFRTYPE: ITU656 Active Video Only Mode */
109 #define EPPI_CTL_ENTIRE656 0x00000004 /* XFRTYPE: ITU656 Entire Field Mode */
110 #define EPPI_CTL_VERT656 0x00000008 /* XFRTYPE: ITU656 Vertical Blanking Only Mode */
111 #define EPPI_CTL_NON656 0x0000000C /* XFRTYPE: Non-ITU656 Mode (GP Mode) */
113 #define EPPI_CTL_SYNC0 0x00000000 /* FSCFG: Sync Mode 0 */
114 #define EPPI_CTL_SYNC1 0x00000010 /* FSCFG: Sync Mode 1 */
115 #define EPPI_CTL_SYNC2 0x00000020 /* FSCFG: Sync Mode 2 */
116 #define EPPI_CTL_SYNC3 0x00000030 /* FSCFG: Sync Mode 3 */
119 #define EPPI_CTL_BLANKGEN 0x00000100 /* ITU Output Mode with Internal Blanking Generation */
151 #define EPPI_CTL_DMACFG 0x10000000 /* One or Two DMA Channels Mode */
H A Dbfin_sdh.h44 #define BUS_MODE_MASK 0x1800 /* Bus Mode Mask */
55 #define DTX_MODE (1 << 2) /* Data Transfer Mode */
133 #define SD_CARD_SLPMODE (1 << 30) /* Card in Sleep Mode */
154 #define BOOT_MODE (1 << 13) /* Alternate Boot Mode */
H A Dbfin_can.h111 #define DNM 0x0002 /* Device Net Mode */
115 #define SMR 0x0020 /* Sleep Mode Request */
116 #define CSR 0x0040 /* CAN Suspend Mode Request */
117 #define CCR 0x0080 /* CAN Configuration Mode Request */
122 #define EP 0x0004 /* Error Passive Mode */
123 #define EBO 0x0008 /* Error Bus Off Mode */
124 #define SMA 0x0020 /* Sleep Mode Acknowledge */
125 #define CSA 0x0040 /* Suspend Mode Acknowledge */
126 #define CCA 0x0080 /* Configuration Mode Acknowledge */
128 #define TRM 0x4000 /* Transmit Mode */
129 #define REC 0x8000 /* Receive Mode */
145 #define MAA 0x0010 /* Mode Auto-Acknowledge Enable */
146 #define MRB 0x0020 /* Mode Read Back Enable */
157 #define SMACK 0x0008 /* Sleep Mode Acknowledge */
661 #define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */
674 #define EPIS 0x0004 /* Error-Passive Mode IRQ Status */
687 #define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */
698 #define UCCNF 0x000F /* Universal Counter Mode */
699 #define UC_STAMP 0x0001 /* Timestamp Mode */
700 #define UC_WDOG 0x0002 /* Watchdog Mode */
701 #define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */
H A Dbfin_serial.h64 #define LOOP_ENA 0x2 /* Loopback Mode Enable */
65 #define UMOD_MDB 0x10 /* Enable MDB Mode */
66 #define UMOD_IRDA 0x20 /* Enable IrDA Mode */
67 #define UMOD_MASK 0x30 /* Uart Mode Mask */
139 #define LOOP_ENA 0x10 /* Loopback Mode Enable */
151 #define UMOD_IRDA 0x02 /* Enable IrDA Mode */
152 #define UMOD_MASK 0x02 /* Uart Mode Mask */
/linux-4.4.14/arch/unicore32/include/mach/
H A Dregs-resetc.h31 * Sleep Mode Reset
H A Dregs-sdc.h29 * Transfer Mode Reg SDC_TMR
/linux-4.4.14/include/linux/bcma/
H A Dbcma_regs.h73 #define BCMA_SOC_PCI_MEM 0x08000000U /* Host Mode sb2pcitranslation0 (64 MB) */
75 #define BCMA_SOC_PCI_CFG 0x0c000000U /* Host Mode sb2pcitranslation1 (64 MB) */
80 #define BCMA_SOC_PCI_DMA 0x40000000U /* Client Mode sb2pcitranslation2 (1 GB) */
81 #define BCMA_SOC_PCI_DMA2 0x80000000U /* Client Mode sb2pcitranslation2 (1 GB) */
82 #define BCMA_SOC_PCI_DMA_SZ 0x40000000U /* Client Mode sb2pcitranslation2 size in bytes */
83 #define BCMA_SOC_PCIE_DMA_L32 0x00000000U /* PCIE Client Mode sb2pcitranslation2
86 #define BCMA_SOC_PCIE_DMA_H32 0x80000000U /* PCIE Client Mode sb2pcitranslation2
90 #define BCMA_SOC_PCI1_MEM 0x40000000U /* Host Mode sb2pcitranslation0 (64 MB) */
91 #define BCMA_SOC_PCI1_CFG 0x44000000U /* Host Mode sb2pcitranslation1 (64 MB) */
92 #define BCMA_SOC_PCIE1_DMA_H32 0xc0000000U /* PCIE Client Mode sb2pcitranslation2
/linux-4.4.14/include/uapi/linux/
H A Dcciss_defs.h60 BYTE Mode:2; /* b00 */ member in struct:_SCSI3Addr_struct::__anon13960
65 BYTE Mode:2; /* b01 */ member in struct:_SCSI3Addr_struct::__anon13961
71 BYTE Mode:2; /* b10 */ member in struct:_SCSI3Addr_struct::__anon13962
78 DWORD Mode:2; member in struct:_PhysDevAddr_struct
84 DWORD Mode:2; member in struct:_LogDevAddr_struct
H A Dscreen_info.h52 #define VIDEO_TYPE_EGAM 0x20 /* EGA/VGA in Monochrome Mode */
53 #define VIDEO_TYPE_EGAC 0x21 /* EGA in Color Mode */
54 #define VIDEO_TYPE_VGAC 0x22 /* VGA+ in Color Mode */
/linux-4.4.14/drivers/staging/rtl8723au/include/
H A Drtw_cmd.h138 Caller Mode: Infra, Ad-HoC(C)
142 Command Mode
150 Caller Mode: Infra, Ad-HoC
154 Command-Event Mode
159 Caller Mode: Infra, Ad-HoC(C)
163 Command Mode
175 Caller Mode: AP, Ad-HoC, Infra
179 Command-Event Mode
194 Caller Mode: Any
198 Command Mode
208 Caller Mode: Infra
283 Caller Mode: AP/Ad-HoC(M)
287 Command Mode
297 Caller Mode: Any
301 Command Mode
309 Caller Mode: Any
313 Command-Rsp Mode
325 Caller Mode: Any
329 Command Mode
338 Caller Mode: Any
342 Command-Rsp Mode
355 Caller Mode: Any
364 Command Mode
383 Caller Mode: Any
388 Command Mode
397 Caller Mode: Any
401 Command-Rsp Mode
H A Drtl8723a_cmd.h62 u8 Mode; member in struct:setpwrmode_parm
145 void rtl8723a_set_FwPwrMode_cmd(struct rtw_adapter *padapter, u8 Mode);
/linux-4.4.14/arch/m32r/include/asm/
H A Dm32r.h83 #define MATM MMU_REG_BASE /* MMU Address Translation Mode
123 #define M32R_PSW_BIT_SM (7) /* Stack Mode */
125 #define M32R_PSW_BIT_PM (3) /* Processor Mode [0:Supervisor,1:User] */
127 #define M32R_PSW_BIT_BSM (7+8) /* Backup Stack Mode */
129 #define M32R_PSW_BIT_BPM (3+8) /* Backup Processor Mode */
133 #define M32R_PSW_SM (1UL<< M32R_PSW_BIT_SM) /* Stack Mode */
135 #define M32R_PSW_PM (1UL<< M32R_PSW_BIT_PM) /* Processor Mode */
137 #define M32R_PSW_BSM (1UL<< M32R_PSW_BIT_BSM) /* Backup Stack Mode */
139 #define M32R_PSW_BPM (1UL<< M32R_PSW_BIT_BPM) /* Backup Processor Mode */
H A Ds1d13806.h18 {0x01FC,0x00}, // Display Mode Register
171 {0x01E0,0x00}, // Look-Up Table Mode Register
177 {0x01FC,0x01}, // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT)
179 {0x01FC,0x41}, // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT)
188 {0x0040,0x05}, // LCD Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
196 {0x0060,0x05}, // CRT/TV Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
/linux-4.4.14/arch/sh/include/cpu-sh4/cpu/
H A Dsh7785.h4 /* Boot Mode Pins:
14 * MODE8: LBSC - Endian Mode (L: Big, H: Little) [BCR.31]
15 * MODE9: LBSC - Master/Slave Mode (L: Slave) [BCR.30]
17 * MODE11: PCI - Pin Mode (LL: PCI host, LH: PCI slave)
18 * MODE12: PCI - Pin Mode (HL: Local bus, HH: DU)
19 * MODE13: Boot Address Mode (L: 29-bit, H: 32-bit)
H A Dsh7722.h4 /* Boot Mode Pins:
6 * MD0: CPG - Clock Mode 0->3
7 * MD1: CPG - Clock Mode 0->3
10 * MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3]
11 * MD8: Test Mode
139 /* Main LCD - RGB Mode */
141 /* Main LCD - SYS Mode */
143 /* Sub LCD - SYS Mode */
H A Dsh7723.h4 /* Boot Mode Pins:
6 * MD0: CPG - Clock Mode 0->3
7 * MD1: CPG - Clock Mode 0->3
10 * MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3]
11 * MD8: Test Mode
155 /* Main LCD - RGB Mode */
157 /* Main LCD - SYS Mode */
H A Dsh7724.h4 /* Boot Mode Pins:
6 * MD0: CPG - Clock Mode 0->7
7 * MD1: CPG - Clock Mode 0->7
8 * MD2: CPG - Clock Mode 0->7
10 * MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3]
11 * MD8: Test Mode
12 * BOOT: FBR - Boot Mode (L: MMCIF, H: Area0)
H A Dcache.h25 #define CCR_CACHE_ORA 0x0020 /* OC RAM Mode */
/linux-4.4.14/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac100.h47 #define MAC_CONTROL_RA 0x80000000 /* Receive All Mode */
48 #define MAC_CONTROL_BLE 0x40000000 /* Endian Mode */
53 #define MAC_CONTROL_OM 0x00200000 /* Loopback Operating Mode */
54 #define MAC_CONTROL_F 0x00100000 /* Full Duplex Mode */
56 #define MAC_CONTROL_PR 0x00040000 /* Promiscuous Mode */
59 #define MAC_CONTROL_HO 0x00008000 /* Hash Only Filtering Mode */
60 #define MAC_CONTROL_HP 0x00002000 /* Hash/Perfect Filtering Mode */
90 /* DMA Bus Mode register defines */
H A Ddwmac_dma.h29 #define DMA_BUS_MODE 0x00001000 /* Bus Mode */
35 #define DMA_CONTROL 0x00001018 /* Ctrl (Operational Mode) */
40 /* AXI Bus Mode */
H A Ddwmac1000.h146 #define GMAC_CONTROL_DM 0x00000800 /* Duplex Mode */
159 #define GMAC_FRAME_FILTER_PR 0x00000001 /* Promiscuous Mode */
181 /* DMA Bus Mode register defines */
208 /* DMA Bus Mode register defines */
/linux-4.4.14/arch/x86/boot/
H A Dvideo-bios.c37 ireg.al = mode; /* AH=0x00 Set Video Mode */ set_bios_mode()
40 ireg.ah = 0x0f; /* Get Current Video Mode */ set_bios_mode()
49 return 0; /* Mode change OK */ set_bios_mode()
53 /* Mode setting failed, but we didn't end up where we set_bios_mode()
H A Dvideo.h63 * Mode table structures
67 u16 mode; /* Mode number (vga= style) */
/linux-4.4.14/arch/sh/kernel/cpu/shmobile/
H A Dcpuidle.c64 .desc = "SuperH Sleep Mode",
72 .desc = "SuperH Sleep Mode [SF]",
81 .desc = "SuperH Mobile Standby Mode [SF]",
/linux-4.4.14/include/linux/mfd/syscon/
H A Datmel-st.h22 #define AT91_ST_PIMR 0x04 /* Period Interval Mode Register */
25 #define AT91_ST_WDMR 0x08 /* Watchdog Mode Register */
30 #define AT91_ST_RTMR 0x0c /* Real-time Mode Register */
/linux-4.4.14/drivers/mfd/
H A Datmel-flexcom.c33 #define FLEX_MR 0x0 /* Mode Register */
36 /* Mode Register bit fields */
37 #define FLEX_MR_OPMODE_OFFSET (0) /* Operating Mode */
74 * Set the Operating Mode in the Mode Register: only the selected device atmel_flexcom_probe()
/linux-4.4.14/drivers/staging/rtl8712/
H A Drtl871x_cmd.h117 * Caller Mode: Infra, Ad-HoC(C)
119 * Command Mode
126 * Caller Mode: Infra, Ad-HoC(C)
128 * Command Mode
135 * Caller Mode: AP, Ad-HoC, Infra
137 * Command Mode
154 * Caller Mode: AP, Ad-HoC, Infra
156 * Command-Event Mode
166 * Caller Mode: Any
168 * Command Mode
177 * Caller Mode: Infra
251 Caller Mode: AP/Ad-HoC(M)
255 Command Mode
265 Caller Mode: Any
269 Command Mode
277 Caller Mode: Any
281 Command-Rsp Mode
293 Caller Mode: Any
297 Command Mode
335 Caller Mode: Any
339 Command-Rsp Mode
352 Caller Mode: Any
361 Command Mode
366 Caller Mode: Any
371 Command Mode
375 Caller Mode: Any
379 Command-Rsp Mode
/linux-4.4.14/drivers/video/fbdev/
H A Dbfin_adv7393fb.h82 0x01, 0x00, /* SD-Only Mode */
83 0x80, 0x10, /* SSAF Luma Filter Enabled, NTSC Mode */
100 0x01, 0x00, /* SD-Only Mode */
101 0x80, 0x30, /* SSAF Luma Filter Enabled, NTSC Mode */
122 0x01, 0x00, /* SD-Only Mode */
123 0x80, 0x11, /* SSAF Luma Filter Enabled, PAL Mode */
138 0x01, 0x00, /* SD-Only Mode */
139 0x80, 0x30, /* SSAF Luma Filter Enabled, NTSC Mode */
154 0x01, 0x00, /* SD-Only Mode */
155 0x80, 0x11, /* SSAF Luma Filter Enabled, PAL Mode */
/linux-4.4.14/drivers/media/i2c/
H A Dadv7343_regs.h92 /* Bit masks for Mode Select Register */
98 /* Bit masks for Mode Register 0 */
109 /* Bit masks for HD Mode Register 1 */
131 /* Bit masks for SD Mode Register 1 */
142 /* Bit masks for SD Mode Register 2 */
155 /* Bit masks for HD Mode Register 6 */
H A Dadv7393_regs.h100 /* Bit masks for Mode Select Register */
106 /* Bit masks for Mode Register 0 */
118 /* Bit masks for HD Mode Register 1 */
140 /* Bit masks for SD Mode Register 1 */
151 /* Bit masks for SD Mode Register 2 */
164 /* Bit masks for HD Mode Register 6 */
H A Dvs6624_regs.h137 #define VS6624_EXPO_TIME_MSB 0x1189 /* exposure time for the Manual Mode MSB */
138 #define VS6624_EXPO_TIME_LSB 0x118A /* exposure time for the Manual Mode LSB */
140 #define VS6624_DIRECT_COARSE_MSB 0x1195 /* coarse integration lines for Direct Mode MSB */
141 #define VS6624_DIRECT_COARSE_LSB 0x1196 /* coarse integration lines for Direct Mode LSB */
142 #define VS6624_DIRECT_FINE_MSB 0x1199 /* fine integration pixels for Direct Mode MSB */
143 #define VS6624_DIRECT_FINE_LSB 0x119A /* fine integration pixels for Direct Mode LSB */
144 #define VS6624_DIRECT_ANAL_GAIN_MSB 0x119D /* analog gain for Direct Mode MSB */
145 #define VS6624_DIRECT_ANAL_GAIN_LSB 0x119E /* analog gain for Direct Mode LSB */
146 #define VS6624_DIRECT_DIGI_GAIN_MSB 0x11A1 /* digital gain for Direct Mode MSB */
147 #define VS6624_DIRECT_DIGI_GAIN_LSB 0x11A2 /* digital gain for Direct Mode LSB */
148 #define VS6624_FLASH_COARSE_MSB 0x11A5 /* coarse integration lines for Flash Gun Mode MSB */
149 #define VS6624_FLASH_COARSE_LSB 0x11A6 /* coarse integration lines for Flash Gun Mode LSB */
150 #define VS6624_FLASH_FINE_MSB 0x11A9 /* fine integration pixels for Flash Gun Mode MSB */
151 #define VS6624_FLASH_FINE_LSB 0x11AA /* fine integration pixels for Flash Gun Mode LSB */
152 #define VS6624_FLASH_ANAL_GAIN_MSB 0x11AD /* analog gain for Flash Gun Mode MSB */
153 #define VS6624_FLASH_ANAL_GAIN_LSB 0x11AE /* analog gain for Flash Gun Mode LSB */
154 #define VS6624_FLASH_DIGI_GAIN_MSB 0x11B1 /* digital gain for Flash Gun Mode MSB */
155 #define VS6624_FLASH_DIGI_GAIN_LSB 0x11B2 /* digital gain for Flash Gun Mode LSB */
H A Dml86v7667.c27 #define MRA_REG 0x00 /* Mode Register A */
28 #define MRC_REG 0x02 /* Mode Register C */
40 /* Mode Register A register bits */
49 /* Mode Register C register bits */
/linux-4.4.14/drivers/media/usb/dvb-usb/
H A Ddib0700.h32 // 1 Byte: 4MSB(1 = enable streaming, 0 = disable streaming) 4LSB(Video Mode: 0 = MPEG2 188Bytes, 1 = Analog)
33 // 2 Byte: MPEG2 mode: 4MSB(1 = Master Mode, 0 = Slave Mode) 4LSB(Channel 1 = bit0, Channel 2 = bit1)
/linux-4.4.14/include/soc/at91/
H A Dat91sam9_sdramc.h20 #define AT91_SDRAMC_MR 0x00 /* SDRAM Controller Mode Register */
21 #define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
69 #define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
H A Dat91sam9_ddrsdr.h15 #define AT91_DDRSDRC_MR 0x00 /* Mode Register */
16 #define AT91_DDRSDRC_MODE (0x7 << 0) /* Command Mode */
87 #define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
115 #define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register [SAM9 Only] */
/linux-4.4.14/drivers/gpu/drm/rcar-du/
H A Drcar_du_kms.h2 * rcar_du_kms.h -- R-Car Display Unit Mode Setting
H A Drcar_du_regs.h330 #define PnMR_BM_MD (0 << 4) /* Manual Display Change Mode */
331 #define PnMR_BM_AR (1 << 4) /* Auto Rendering Mode */
332 #define PnMR_BM_AD (2 << 4) /* Auto Display Change Mode */
333 #define PnMR_BM_VC (3 << 4) /* Video Capture Mode */
404 #define APnMR_BM_MD (0 << 4) /* Manual Display Change Mode */
405 #define APnMR_BM_AD (2 << 4) /* Auto Display Change Mode */
/linux-4.4.14/drivers/gpu/drm/shmobile/
H A Dshmob_drm_kms.h2 * shmob_drm_kms.h -- SH Mobile DRM Mode Setting
H A Dshmob_drm_kms.c2 * shmob_drm_kms.c -- SH Mobile DRM Mode Setting
/linux-4.4.14/drivers/platform/x86/
H A Ddell-rbtn.h2 Dell Airplane Mode Switch driver
/linux-4.4.14/include/linux/
H A Dsmc91x.h22 #define RPC_LED_FD (0x03) /* LED = Full Duplex Mode */
H A Dsmscphy.h6 #define MII_LAN83C185_CTRL_STATUS 17 /* Mode/Status Register */
H A Datmel_serial.h44 #define ATMEL_US_MR 0x04 /* Mode Register */
45 #define ATMEL_US_USMODE GENMASK(3, 0) /* Mode of the USART */
62 #define ATMEL_US_SYNC BIT(8) /* Synchronous Mode Select */
74 #define ATMEL_US_CHMODE GENMASK(15, 14) /* Channel Mode */
82 #define ATMEL_US_OVER BIT(19) /* Oversampling Mode */
133 #define ATMEL_US_FMR 0xa0 /* FIFO Mode Register */
134 #define ATMEL_US_TXRDYM(data) (((data) & 0x3) << 0) /* TX Ready Mode */
135 #define ATMEL_US_RXRDYM(data) (((data) & 0x3) << 4) /* RX Ready Mode */
H A Dconsole_struct.h72 unsigned int vc_decscnm : 1; /* Screen Mode */
73 unsigned int vc_decom : 1; /* Origin Mode */
74 unsigned int vc_decawm : 1; /* Autowrap Mode */
76 unsigned int vc_decim : 1; /* Insert Mode */
77 unsigned int vc_deccolm : 1; /* 80/132 Column Mode */
H A Datmel-ssc.h43 /* SSC Clock Mode Register */
48 /* SSC Receive Clock Mode Register */
67 /* SSC Receive Frame Mode Register */
90 /* SSC Transmit Clock Mode Register */
107 /* SSC Transmit Frame Mode Register */
H A Dfsl_ifc.h132 * Chip Select Option Register - NOR Flash Mode
134 /* Enable Address shift Mode */
159 * Chip Select Option Register - GPCM Mode
161 /* GPCM Mode - Normal */
163 /* GPCM Mode - GenericASIC */
165 /* Parity Mode odd/even */
271 /* Auto Boot Mode */
273 /* Addressing Mode-ROW0+n/COL0 */
275 /* Addressing Mode-ROW0+n/COL0+n */
/linux-4.4.14/arch/arm/mach-pxa/include/mach/
H A Dpxa2xx-regs.h90 #define PSSR_STS (1 << 3) /* Standby Mode Status */
95 #define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
100 #define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */
105 #define PCFR_DS (1 << 3) /* Deep Sleep Mode */
111 #define RCSR_SMR (1 << 2) /* Sleep Mode */
142 #define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
143 #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
H A Dregs-u2d.h60 #define U2DOTGCR_CKAF (1 << 5) /* Carkit Mode Alternate Function Select */
62 #define U2DOTGCR_ULAF (1 << 3) /* ULPI Mode Alternate Function Select */
63 #define U2DOTGCR_SMAF (1 << 2) /* Serial Mode Alternate Function Select */
64 #define U2DOTGCR_RTSM (1 << 1) /* Return to Synchronous Mode (ULPI Mode) */
88 #define U2DOTGUSR_LPA (1 << 31) /* ULPI Low Power Mode Active */
89 #define U2DOTGUSR_S6A (1 << 30) /* ULPI Serial Mode (6-pin) Active */
90 #define U2DOTGUSR_S3A (1 << 29) /* ULPI Serial Mode (3-pin) Active */
91 #define U2DOTGUSR_CKA (1 << 28) /* ULPI Car Kit Mode Active */
108 #define U2DP3CR_P2SS (0x3 << 8) /* Host Port 2 Serial Mode Select */
109 #define U2DP3CR_P3SS (0x7 << 4) /* Host Port 3 Serial Mode Select */
H A Dpxa3xx-regs.h139 #define ACCR_D0CS (1 << 26) /* D0 Mode Clock Select */
140 #define ACCR_PCCE (1 << 11) /* Power Mode Change Clock Enable */
148 #define ACCR_XN_MASK (0x7 << 8) /* Core PLL Turbo-Mode-to-Run-Mode Ratio */
149 #define ACCR_XL_MASK (0x1f) /* Core PLL Run-Mode-to-Oscillator Ratio */
/linux-4.4.14/arch/arm/mach-ixp4xx/include/mach/
H A Dixp46x_ts.h51 u32 asms_lo; /* 0x30 Auxiliary Slave Mode Snapshot Low */
52 u32 asms_hi; /* 0x34 Auxiliary Slave Mode Snapshot High */
53 u32 amms_lo; /* 0x38 Auxiliary Master Mode Snapshot Low */
54 u32 amms_hi; /* 0x3C Auxiliary Master Mode Snapshot High */
/linux-4.4.14/sound/ppc/
H A Dawacs.h60 #define MASK_EXMODEADDR (0x3ff << 12) /* Extended Mode Address -- 10 bits */
61 #define MASK_EXMODEDATA (0xfff) /* Extended Mode Data -- 12 bits */
65 #define MASK_ADDR0 (0x0 << 12) /* Expanded Data Mode Address 0 */
69 #define MASK_ADDR1 (0x1 << 12) /* Expanded Data Mode Address 1 */
73 #define MASK_ADDR2 (0x2 << 12) /* Expanded Data Mode Address 2 */
77 #define MASK_ADDR4 (0x4 << 12) /* Expanded Data Mode Address 4 */
82 #define MASK_ADDR5 (0x5 << 12) /* Expanded Data Mode Address 5 */
83 #define MASK_ADDR6 (0x6 << 12) /* Expanded Data Mode Address 6 */
84 #define MASK_ADDR7 (0x7 << 12) /* Expanded Data Mode Address 7 */
/linux-4.4.14/include/video/
H A Dda8xx-fb.h59 /* 12 Bit Per Pixel (5-6-5) Mode (Only for passive) */
62 /* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */
H A Dw100fb.h69 /* LCD Mode definition */
127 /* Initial Mode flags */
H A Ds1d13xxxfb.h53 #define S1DREG_LCD_DISP_MODE 0x0040 /* LCD Display Mode Register */
73 #define S1DREG_CRT_DISP_MODE 0x0060 /* CRT/TV Display Mode Register */
128 #define S1DREG_LKUP_MODE 0x01E0 /* Look-Up Table Mode Register */
134 #define S1DREG_COM_DISP_MODE 0x01FC /* Common Display Mode Register */
H A Duvesafb.h30 /* VBE Mode Info Block */
/linux-4.4.14/arch/mips/include/asm/
H A Dtxx9tmr.h46 /* TMITMR : Interval Timer Mode */
50 /* TMWTMR : Watchdog Timer Mode */
H A Djazzdma.h60 #define JAZZ_R4030_CHNL_MODE 0xE0000100 /* 8 DMA Channel Mode Registers, */
/linux-4.4.14/arch/m68k/include/asm/
H A Dmcftimer.h18 #define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */
29 * Bit definitions for the Timer Mode Register (TMR).
H A Dmcfdma.h72 #define MCFDMA_DMR 0x00 /* Mode Register (r/w) */
78 /* Bit definitions for the DMA Mode Register (DMR) */
81 #define MCFDMA_DMR_RQM 0x000C0000L /* Request Mode Mask */
H A Dm520xsim.h73 #define MCFSIM_SDMR 0xFC0a8000 /* SDRAM Mode/Extended Mode Register */
/linux-4.4.14/arch/arm/mach-sa1100/include/mach/
H A Dnanoengine.h39 * 4000.0000 - 47FF.FFFF - 128 MB External Bus I/O - Multiplexed Mode
40 * 4800.0000 - 4FFF.FFFF - 128 MB External Bus I/O - Non-Multiplexed Mode
/linux-4.4.14/arch/arm/mach-cns3xxx/
H A Ddevices.c58 tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */ cns3xxx_ahci_init()
59 tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */ cns3xxx_ahci_init()
/linux-4.4.14/drivers/media/platform/s5p-g2d/
H A Dg2d-regs.h18 #define AXI_ID_MODE_REG 0x0014 /* AXI Read ID Mode reg */
20 #define AXI_MODE_REG 0x001C /* AXI Mode reg */
35 #define SRC_COLOR_MODE_REG 0x030C /* Src Image Color Mode reg */
46 #define DST_COLOR_MODE_REG 0x040C /* Dest Image Color Mode reg */
53 #define PAT_COLOR_MODE_REG 0x0508 /* Pattern Image Color Mode reg */
/linux-4.4.14/drivers/cpufreq/
H A Delanfreq.c39 int val40h; /* PMU Force Mode register */
76 * the normal way, 66 and 99 MHz are called "Hyperspeed Mode"
119 * 0x40 is the Power Management Unit's Force Mode Register. elanfreq_target()
120 * Bit 6 enables Hyperspeed Mode (66/100 MHz core frequency) elanfreq_target()
135 /* now, the hyperspeed bit in PMU Force Mode Register (0x40) */ elanfreq_target()
/linux-4.4.14/include/linux/spi/
H A Dadi_spi3.h25 #define SPI_CTL_ODM 0x00000008 /* Open Drain Mode */
44 #define SPI_CTL_MIOM 0x00300000 /* Multiple I/O Mode */
46 #define SPI_CTL_MIO_DUAL 0x00100000 /* MIOM: Enable DIOM (Dual I/O Mode) */
47 #define SPI_CTL_MIO_QUAD 0x00200000 /* MIOM: Enable QUAD (Quad SPI Mode) */
130 #define SPI_IMSK_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */
141 #define SPI_IMSK_CLR_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */
152 #define SPI_IMSK_SET_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */
164 #define SPI_STAT_MODF 0x00000080 /* Mode Fault Error Indication */
190 #define SPI_ILAT_MFI 0x00000080 /* Mode Fault Error Indication */
201 #define SPI_ILAT_CLR_MFI 0x00000080 /* Mode Fault Error Indication */
/linux-4.4.14/drivers/staging/rtl8188eu/include/
H A Drtw_cmd.h105 Caller Mode: Infra, Ad-HoC(C)
109 Command Mode
122 Caller Mode: AP, Ad-HoC, Infra
126 Command-Event Mode
141 Caller Mode: Any
145 Command Mode
155 Caller Mode: Infra
232 Caller Mode: AP/Ad-HoC(M)
236 Command Mode
H A Drtl8188e_cmd.h68 u8 Mode;/* 0:Active,1:LPS,2:WMMPS */ member in struct:setpwrmode_parm
108 void rtl8188e_set_FwPwrMode_cmd(struct adapter *padapter, u8 Mode);
/linux-4.4.14/drivers/staging/vt6655/
H A Dpower.c29 * PSvEnablePowerSaving - Enable Power Saving Mode
30 * PSvDiasblePowerSaving - Disable Power Saving Mode
105 pr_debug("PS:Power Saving Mode Enable...\n"); PSvEnablePowerSaving()
/linux-4.4.14/drivers/staging/vt6656/
H A Dpower.c29 * vnt_enable_power_saving - Enable Power Saving Mode
30 * PSvDiasblePowerSaving - Disable Power Saving Mode
92 dev_dbg(&priv->usb->dev, "PS:Power Saving Mode Enable...\n"); vnt_enable_power_saving()
/linux-4.4.14/drivers/hid/
H A Dhid-betopff.c8 * - tested with BTP2185 BFM Mode.
11 * - tested with BTP2185 PC Mode.
14 * - tested with BTP2185 PC Mode with another version.
/linux-4.4.14/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_dcb_82599.h39 #define IXGBE_RTTDCS_TDRM 0x00000010 /* Transmit Recycle Mode */
66 #define IXGBE_RTRPCS_RRM 0x00000002 /* Receive Recycle Mode enable */
87 #define IXGBE_RTTPCS_TPRM 0x00000100 /* Transmit Recycle Mode enable */
H A Dixgbe_dcb_82598.h36 #define IXGBE_DPMCS_TRM 0x00000010 /* Transmit Recycle Mode */
60 #define IXGBE_PDPMCS_TRM 0x00000100 /* Transmit Recycle Mode enable */
/linux-4.4.14/arch/blackfin/mach-bf548/include/mach/
H A Danomaly.h30 /* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
40 /* FIFO Boot Mode Not Functional */
60 /* 16-Bit NAND FLASH Boot Mode Is Not Functional */
76 /* NAND Boot Mode Not Compatible With Some NAND Flash Devices */
108 /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
112 /* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
170 /* TWI Slave Boot Mode Is Not Functional */
176 /* Synchronous Burst Flash Boot Mode Is Not Functional */
188 /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
214 /* 8-Bit NAND Flash Boot Mode Not Functional */
228 /* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
/linux-4.4.14/drivers/scsi/pcmcia/
H A Dnsp_debug.c21 /* 13-16 */ unknown, "Recover Buffered Data", "Mode Select", "Reserve",
22 /* 17-1b */ "Release", "Copy", "Erase", "Mode Sense", "Start/Stop Unit",
44 /* 50-55 */ unknown, unknown, unknown, unknown, unknown, "Mode Select (10)",
45 /* 56-5b */ unknown, unknown, unknown, unknown, "Mode Sense (10)", unknown,
/linux-4.4.14/drivers/staging/comedi/drivers/
H A Dssv_dnp.c38 /* 0..3 remain unchanged! For details about Port C Mode Register see */
43 #define PAMR 0xa5 /* Port A Mode Register */
45 #define PBMR 0xa4 /* Port B Mode Register */
47 #define PCMR 0xa3 /* Port C Mode Register */
H A Ds526.c187 * data[1]: Counter Mode Register Value s526_gpct_insn_config()
194 /* Set Counter Mode Register */ s526_gpct_insn_config()
231 /* Set Counter Mode Register */ s526_gpct_insn_config()
256 * data[1]: Counter Mode Register Value s526_gpct_insn_config()
263 /* Set Counter Mode Register */ s526_gpct_insn_config()
271 /* Set Counter Mode Register */ s526_gpct_insn_config()
289 * data[1]: Counter Mode Register Value s526_gpct_insn_config()
296 /* Set Counter Mode Register */ s526_gpct_insn_config()
304 /* Set Counter Mode Register */ s526_gpct_insn_config()
/linux-4.4.14/drivers/gpu/drm/via/
H A Dvia_dmablit.h107 #define VIA_PCI_DMA_MR0 0xE80 /* Mode Register of Channel 0 */
108 #define VIA_PCI_DMA_MR1 0xE84 /* Mode Register of Channel 1 */
109 #define VIA_PCI_DMA_MR2 0xE88 /* Mode Register of Channel 2 */
110 #define VIA_PCI_DMA_MR3 0xE8C /* Mode Register of Channel 3 */
/linux-4.4.14/drivers/parisc/
H A Dccio-rm-dma.c4 * "Real Mode" operation refers to U2/Uturn chip operation. The chip
10 * Drawbacks of using Real Mode are:
175 ** in "Real Mode". ccio_probe()
179 /* will need this for "Virtual Mode" operation */ ccio_probe()
/linux-4.4.14/include/media/
H A Dov772x.h22 * strength also control Auto or Manual Edge Control Mode
H A Dadv7842.h67 /* Mode of operation */
196 /* 0 = Mode 0: run when there is no TMDS clock
197 1 = Mode 1: run when there is no TMDS clock or the
H A Dsaa7115.h72 * Should be set to "Fast Locking Mode" according to the datasheet,
74 * saa7113_init sets this value to "VTR Mode". */
/linux-4.4.14/include/linux/can/platform/
H A Dcc770.h8 #define CPUIF_PWD 0x10 /* Power Down Mode */
/linux-4.4.14/include/linux/platform_data/
H A Dserial-omap.h34 bool dma_enabled; /* To specify DMA Mode */
H A Dbfin_rotary.h53 #define CNTMODE (0x7 << CNTMODE_SHIFT) /* Counter Operating Mode */
56 #define BNDMODE (0x3 << BNDMODE_SHIFT) /* Boundary register Mode */
H A Dvideo-pxafb.h80 /* Parallel Mode Timing */
90 /* Smart Panel Mode Timing - see PXA27x DM 7.4.15.0.3 for details
/linux-4.4.14/arch/sparc/include/asm/
H A Dfhc.h46 #define FHC_CONTROL_AOFF 0x00001000 /* CPU A SRAM/SBD Low Power Mode */
47 #define FHC_CONTROL_BOFF 0x00000800 /* CPU B SRAM/SBD Low Power Mode */
61 #define FHC_BSR_NDIAG 0x00000040 /* Not in Diag Mode */
62 #define FHC_BSR_NTBED 0x00000020 /* Not in TestBED Mode */
H A Dross.h30 * BM: Boot-Mode. One indicates the MMU is in boot mode.
36 * CM: Cache Mode -- 0 = write-through, 1 = copy-back
/linux-4.4.14/drivers/watchdog/
H A Dat91sam9_wdt.h23 #define AT91_WDT_MR 0x04 /* Watchdog Mode Register */
/linux-4.4.14/include/linux/mfd/da9055/
H A Dpdata.h28 /* Enable RTC in RESET Mode */
/linux-4.4.14/drivers/rtc/
H A Drtc-at91rm9200.h32 #define AT91_RTC_MR 0x04 /* Mode Register */
33 #define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */
/linux-4.4.14/drivers/media/rc/keymaps/
H A Drc-budget-ci-old.c18 * Zenith Universal 7 / TV Mode 807 / VCR Mode 837
/linux-4.4.14/arch/sh/include/cpu-sh5/cpu/
H A Dcache.h53 #define OCCR0_WT 0x4 /* Set OCACHE in WT Mode */
54 #define OCCR0_WB 0x0 /* Set OCACHE in WB Mode */
/linux-4.4.14/arch/blackfin/mach-bf537/include/mach/
H A Danomaly.h52 /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
58 /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
92 /* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */
122 /* EMAC RMII Mode: Collisions Occur in Full Duplex Mode */
124 /* EMAC RMII Mode: TX Frames in Half Duplex Fail with Status "No Carrier" */
126 /* EMAC RMII Mode at 10-Base-T Speed: RX Frames Not Received Properly */
138 /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
H A DdefBF537.h18 #define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
169 #define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
170 #define PR 0x00000080 /* Promiscuous Mode Enable */
175 #define RAF 0x00001000 /* Receive-All Mode */
187 #define RMII 0x01000000 /* RMII/MII* Mode */
189 #define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
191 #define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
323 #define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
/linux-4.4.14/drivers/ipack/devices/
H A Dscc2698.h26 u8 d0, mr; /* Mode register 1/2*/
33 u8 d0, mr; /* Mode register 1/2 */
51 u8 d0, mra; /* Mode register 1/2 (a) */
59 u8 d8, mrb; /* Mode register 1/2 (b) */
69 u8 d0, mra; /* Mode register 1/2 (a) */
77 u8 d8, mrb; /* Mode register 1/2 (b) */
/linux-4.4.14/drivers/net/ethernet/marvell/
H A Dskge.h632 MFF_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
633 MFF_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
775 RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
776 RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
908 XMR_FS_BURST = 1<<11, /* Bit 11: Burst Mode */
1023 PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
1024 PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
1026 PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
1105 PHY_X_P_NO_PAUSE= 0<<7,/* Bit 8..7: no Pause Mode */
1106 PHY_X_P_SYM_MD = 1<<7, /* Bit 8..7: symmetric Pause Mode */
1107 PHY_X_P_ASYM_MD = 2<<7,/* Bit 8..7: asymmetric Pause Mode */
1108 PHY_X_P_BOTH_MD = 3<<7,/* Bit 8..7: both Pause Mode */
1120 PHY_X_RS_PAUSE = 3<<7, /* Bit 8..7: selected Pause Mode */
1121 PHY_X_RS_HD = 1<<6, /* Bit 6: Half Duplex Mode selected */
1122 PHY_X_RS_FD = 1<<5, /* Bit 5: Full Duplex Mode selected */
1179 PHY_B_PEC_EN_LTR = 1<<5, /* Bit 5: Ena LED Traffic Mode */
1182 PHY_B_PEC_EX_IPG = 1<<2, /* Bit 2: Extend Tx IPG Mode */
1234 PHY_B_AC_DIAG = 1<<3, /* Bit 3: Diagnostic Mode */
1270 PHY_B_IS_DUP_CHANGE = 1<<3, /* Bit 3: Duplex Mode Change */
1281 PHY_B_P_NO_PAUSE = 0<<10,/* Bit 11..10: no Pause Mode */
1282 PHY_B_P_SYM_MD = 1<<10, /* Bit 11..10: symmetric Pause Mode */
1283 PHY_B_P_ASYM_MD = 2<<10,/* Bit 11..10: asymmetric Pause Mode */
1284 PHY_B_P_BOTH_MD = 3<<10,/* Bit 11..10: both Pause Mode */
1320 PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
1321 PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
1322 PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
1323 PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
1353 PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */
1354 PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
1409 PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */
1528 PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
1630 GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
1720 GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
1721 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
1731 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
1732 GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
1737 GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
1738 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
1741 GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
1742 GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
1743 GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
1746 GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
1747 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
1792 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1821 GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
1822 GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
1864 GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
1865 GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
1868 GMF_OPER_ON = 1<<3, /* Operational Mode On */
1869 GMF_OPER_OFF = 1<<2, /* Operational Mode Off */
1897 GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */
1898 GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */
2047 XM_MODE = 0x0124, /* 32 bit r/w Mode Register */
2124 XM_MMU_GMII_LOOP= 1<<2, /* Bit 2: PHY is in Loopback Mode */
2133 XM_TX_ENC_BYP = 1<<5, /* Bit 5: Set Encoder in Bypass Mode */
2160 XM_RX_TP_MD = 1<<5, /* Bit 5: Enable transparent Mode */
2248 /* XM_MODE 32 bit r/w Mode Register */
2253 XM_MD_TX_REP = 1<<24, /* Bit 24: Transmit Repeater Mode */
H A Dsky2.h34 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
35 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
106 P_ASPM_A1_MODE_SELECT = 1<<2, /* A1 Mode Select (A1 only) */
192 PSM_CONFIG_REG1_PTP_MODE = 1<<28, /* PTP Mode */
609 CFG_LED_MODE_MSK = 7<<2, /* Bit 4.. 2: LED Mode Mask */
648 PEX_RD_ACCESS = 1<<31, /* Access Mode Read = 1, Write = 0 */
972 RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
973 RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
996 ECU_JUMBO_WM = 0x0080, /* Jumbo Mode Watermark */
1185 PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
1186 PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
1188 PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
1293 PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
1294 PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
1295 PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
1296 PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
1326 PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */
1327 PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
1390 PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */
1542 PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
1613 PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */
1643 GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
1732 GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
1733 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
1743 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
1744 GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
1749 GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
1750 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
1753 GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
1754 GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
1755 GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
1758 GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
1759 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
1806 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1839 GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
1840 GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
1897 GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
1898 GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
1902 GMF_OPER_ON = 1<<3, /* Operational Mode On */
1903 GMF_OPER_OFF = 1<<2, /* Operational Mode Off */
1939 TX_PCI_JUM_ENA = 1<<23,/* PCI Jumbo Mode enable */
1940 TX_PCI_JUM_DIS = 1<<22,/* PCI Jumbo Mode enable */
1987 HCU_CCSR_CPU_RST_MODE = 1<<8, /* CPU Reset Mode */
2012 SC_STAT_OP_ON = 1<<3, /* Operational Mode On */
2013 SC_STAT_OP_OFF = 1<<2, /* Operational Mode Off */
2029 GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */
2030 GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */
/linux-4.4.14/drivers/ata/
H A Dpata_at32.c40 * True IDE Mode: 00c0 0000 -> 00df ffff
41 * Alt IDE Mode: 00e0 0000 -> 00ff ffff
63 * Mode 0 | 3.3 | 600 ns | 0x01
64 * Mode 1 | 5.2 | 383 ns | 0x03
65 * Mode 2 | 8.3 | 240 ns | 0x07
66 * Mode 3 | 11.1 | 180 ns | 0x0f
67 * Mode 4 | 16.7 | 120 ns | 0x1f
H A Dpata_sch.c44 PM = 0x07, /* PIO Mode Bit Mask */
45 MDM = (0x03 << 8), /* Multi-word DMA Mode Bit Mask */
46 UDM = (0x07 << 16), /* Ultra DMA Mode Bit Mask */
/linux-4.4.14/arch/mips/include/asm/mach-pmcs-msp71xx/
H A Dmsp_gpio_macros.h116 0xffffffff, /* Mode 0 - INPUT */
117 0x00000, /* Mode 1 - INTERRUPT */
118 0x00030, /* Mode 2 - UART_INPUT (GPIO 4, 5)*/
120 0xffffffff, /* Mode 8 - OUTPUT */
121 0x0000f, /* Mode 9 - UART_OUTPUT/
123 0x00003, /* Mode a - PERF_TIMERB (GPIO 0, 1) */
124 0x00000, /* Mode b - Not really a mode! */
/linux-4.4.14/arch/mips/txx9/rbtx4939/
H A Dsetup.c296 /* BOOT Mode: USER ROM1 / USER ROM2 */ rbtx4939_flash_fixup_ofs()
303 /* BOOT Mode: Monitor ROM */ rbtx4939_flash_fixup_ofs()
335 /* BOOT Mode: USER ROM1 / USER ROM2 */ rbtx4939_flash_copy_from()
352 /* BOOT Mode: Monitor ROM */ rbtx4939_flash_copy_from()
388 /* BOOT Mode: USER ROM1 / USER ROM2 */ rbtx4939_mtd_init()
397 /* BOOT Mode: Monitor ROM */ rbtx4939_mtd_init()
407 /* BOOT Mode: ROM Emulator */ rbtx4939_mtd_init()
/linux-4.4.14/arch/blackfin/mach-bf561/include/mach/
H A Danomaly.h36 /* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
64 /* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */
88 /* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */
102 /* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
112 /* SPORT Data Transmit Lines Are Incorrectly Driven in Multichannel Mode */
122 /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
128 /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
204 /* 24-Bit SPI Boot Mode Is Not Functional */
206 /* Slave SPI Boot Mode Is Not Functional */
220 /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
268 /* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
298 /* Frame Delay in SPORT Multichannel Mode */
/linux-4.4.14/drivers/clk/pxa/
H A Dclk-pxa25x.c41 /* Memory Frequency to Run Mode Frequency Multiplier (M) */
44 /* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
74 pr_info("Run Mode clock: %ld.%02ldMHz\n", pxa25x_get_clk_frequency_khz()
76 pr_info("Turbo Mode clock: %ld.%02ldMHz\n", pxa25x_get_clk_frequency_khz()
/linux-4.4.14/drivers/usb/storage/
H A Dsierra_ms.c142 usb_stor_dbg(us, "SWIMS: Forcing Modem Mode\n"); sierra_ms_init()
150 usb_stor_dbg(us, "SWIMS: Forcing Mass Storage Mode\n"); sierra_ms_init()
184 usb_stor_dbg(us, "SWIMS: Switching to Modem Mode\n"); sierra_ms_init()
H A Doption_ms.c157 usb_stor_dbg(us, "Option MS: %s\n", "Forcing Modem Mode"); option_ms_init()
166 "Allowing Mass Storage Mode if device requests it"); option_ms_init()
/linux-4.4.14/drivers/staging/fbtft/
H A Dfb_ssd1306.c80 /* Set Memory Addressing Mode */ init_display()
128 /* Set Lower Column Start Address for Page Addressing Mode */ set_addr_win()
130 /* Set Higher Column Start Address for Page Addressing Mode */ set_addr_win()
/linux-4.4.14/drivers/input/mouse/
H A Dtrackpoint.h41 * Mode manipulation
45 #define TP_SET_HARD_TRANS 0x45 /* Mode can only be set */
88 #define TP_TOGGLE_BURST 0x28 /* Burst Mode */
H A Dcypress_ps2.h47 * report mode bit is set, firmware working in Remote Mode.
48 * report mode bit is cleared, firmware working in Stream Mode.
/linux-4.4.14/drivers/net/usb/
H A Dsr9800.h80 /* command : Monitor Mode Status Read Reg */
82 /* command : Monitor Mode Status Write Reg */
136 /* Medium Status Default Mode */
/linux-4.4.14/include/net/irda/
H A Dirlap_frame.h46 #define SNRM_CMD 0x83 /* Set Normal Response Mode */
52 #define RNRM_RSP 0x83 /* Request Normal Response Mode */
55 #define DM_RSP 0x0f /* Disconnect Mode */
/linux-4.4.14/include/linux/mtd/
H A Dpfow.h134 printk(KERN_NOTICE"DSR.9,8: (10) Object Mode Program attempt " print_drs_error()
135 "in region with Control Mode data\n"); print_drs_error()
138 "with Object Mode data\n"); print_drs_error()
/linux-4.4.14/arch/blackfin/include/uapi/asm/
H A Dbfin_sport.h124 #define MCCRM 0x0003 /* Multichannel Clock Recovery Mode */
125 #define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
130 #define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
/linux-4.4.14/include/linux/mfd/arizona/
H A Dpdata.h90 /** Mode for primary IRQ (defaults to active low) */
166 * Mode of input structures
173 /** Mode for outputs */
/linux-4.4.14/drivers/ide/
H A Dpalm_bk3710.c69 { 160, 240 / 2 }, /* UDMA Mode 0 */
70 { 125, 160 / 2 }, /* UDMA Mode 1 */
71 { 100, 120 / 2 }, /* UDMA Mode 2 */
72 { 100, 90 / 2 }, /* UDMA Mode 3 */
73 { 100, 60 / 2 }, /* UDMA Mode 4 */
74 { 85, 40 / 2 }, /* UDMA Mode 5 */
/linux-4.4.14/drivers/net/hamradio/
H A Dz8530.h57 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
59 #define ENT_HM 0x10 /* Enter Hunt Mode */
78 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
79 #define EXTSYNC 0x30 /* External Sync Mode */
128 /* Write Register 11 (Clock Mode control) */
230 #define FASTDTR 0x10 /* Fast DTR/REQ Mode */
/linux-4.4.14/drivers/net/wan/lmc/
H A Dlmc_var.h382 #define PROMISC_MODE 0x00000040 /* Promiscuous Mode */
396 * aSR6 -- Command (Operation Mode) Register
400 #define TULIP_CMD_TXTHRSHLDCTL 0x00400000L /* (RW) Transmit Threshold Mode (21140) */
404 #define TULIP_CMD_FULLDUPLEX 0x00000200L /* (RW) Full Duplex Mode */
405 #define TULIP_CMD_OPERMODE 0x00000C00L /* (RW) Operating Mode */
406 #define TULIP_CMD_PROMISCUOUS 0x00000041L /* (RW) Promiscuous Mode */
/linux-4.4.14/drivers/media/tuners/
H A Dmxl5005s.c243 u8 Mode; /* 0: Analog Mode ; 1: Digital Mode */ member in struct:mxl5005s_state
244 u8 IF_Mode; /* for Analog Mode, 0: zero IF; 1: low IF */
250 u8 AGC_Mode; /* AGC Mode 0: Dual AGC; 1: Single AGC */
1672 u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ MXL5005_TunerConfig()
1673 u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ MXL5005_TunerConfig()
1677 u8 AGC_Mode, /* AGC Mode - Dual AGC: 0, Single AGC: 1 */ MXL5005_TunerConfig()
1696 state->Mode = Mode; MXL5005_TunerConfig()
1723 if (state->Mode == 1) /* Digital Mode */ MXL_SynthIFLO_Calc()
1725 else /* Analog Mode */ { MXL_SynthIFLO_Calc()
1737 if (state->Mode == 1) /* Digital Mode */ { MXL_SynthRFTGLO_Calc()
1742 } else /* Analog Mode */ { MXL_SynthRFTGLO_Calc()
1774 status += MXL_ControlWrite(fe, DN_IQTN_AMP_CUT, state->Mode ? 1 : 0); MXL_BlockInit()
1777 status += MXL_ControlWrite(fe, BB_MODE, state->Mode ? 0 : 1); MXL_BlockInit()
1778 status += MXL_ControlWrite(fe, BB_BUF, state->Mode ? 3 : 2); MXL_BlockInit()
1779 status += MXL_ControlWrite(fe, BB_BUF_OA, state->Mode ? 1 : 0); MXL_BlockInit()
1780 status += MXL_ControlWrite(fe, BB_IQSWAP, state->Mode ? 0 : 1); MXL_BlockInit()
1784 if (state->Mode) { /* Digital Mode */ MXL_BlockInit()
1797 } else { /* Analog Mode */ MXL_BlockInit()
1815 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, state->Mode ? 5 : 8); MXL_BlockInit()
1817 RFSYN_EN_CHP_HIGAIN, state->Mode ? 1 : 1); MXL_BlockInit()
1818 status += MXL_ControlWrite(fe, EN_CHP_LIN_B, state->Mode ? 0 : 0); MXL_BlockInit()
1824 } else /* Single AGC Mode Dig Ana */ MXL_BlockInit()
1825 status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12); MXL_BlockInit()
1888 if (state->Mode) { /* Digital Mode */ MXL_BlockInit()
1908 } else { /* Analog Mode */ MXL_BlockInit()
1951 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog LowIF mode */ MXL_BlockInit()
1984 if (state->Mod_Type == MXL_DVBT) /* DVB-T Mode */ { MXL_BlockInit()
1985 state->AGC_Mode = 1; /* Single AGC Mode */ MXL_BlockInit()
2007 if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */ { MXL_BlockInit()
2008 state->AGC_Mode = 1; /* Single AGC Mode */ MXL_BlockInit()
2033 if (state->Mod_Type == MXL_QAM) /* QAM Mode */ { MXL_BlockInit()
2034 state->Mode = MXL_DIGITAL_MODE; MXL_BlockInit()
2036 /* state->AGC_Mode = 1; */ /* Single AGC Mode */ MXL_BlockInit()
2059 /* Analog Cable Mode */ MXL_BlockInit()
2060 /* state->Mode = MXL_DIGITAL_MODE; */ MXL_BlockInit()
2062 state->AGC_Mode = 1; /* Single AGC Mode */ MXL_BlockInit()
2077 /* state->Mode = MXL_ANALOG_MODE; */ MXL_BlockInit()
2119 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF mode */ { MXL_IFSynthInit()
2162 if (state->Mode || (state->Mode == 0 && state->IF_Mode == 0)) { MXL_IFSynthInit()
3689 if (state->Mode == 0 && state->IF_Mode == 1) { MXL_VCORange_Test()
3690 /* Analog Low IF Mode */ MXL_VCORange_Test()
3697 if (state->Mode == 0 && state->IF_Mode == 0) { MXL_VCORange_Test()
3698 /* Analog Zero IF Mode */ MXL_VCORange_Test()
3705 if (state->Mode == 1) /* Digital Mode */ { MXL_VCORange_Test()
3725 if (state->Mode == 0 && state->IF_Mode == 1) { MXL_VCORange_Test()
3726 /* Analog Low IF Mode */ MXL_VCORange_Test()
3733 if (state->Mode == 0 && state->IF_Mode == 0) { MXL_VCORange_Test()
3734 /* Analog Zero IF Mode */ MXL_VCORange_Test()
3741 if (state->Mode == 1) /* Digital Mode */ { MXL_VCORange_Test()
3761 if (state->Mode == 0 && state->IF_Mode == 1) { MXL_VCORange_Test()
3762 /* Analog Low IF Mode */ MXL_VCORange_Test()
3769 if (state->Mode == 0 && state->IF_Mode == 0) { MXL_VCORange_Test()
3770 /* Analog Zero IF Mode */ MXL_VCORange_Test()
3777 if (state->Mode == 1) /* Digital Mode */ { MXL_VCORange_Test()
3797 if (state->Mode == 0 && state->IF_Mode == 1) { MXL_VCORange_Test()
3798 /* Analog Low IF Mode */ MXL_VCORange_Test()
3805 if (state->Mode == 0 && state->IF_Mode == 0) { MXL_VCORange_Test()
3806 /* Analog Zero IF Mode */ MXL_VCORange_Test()
3813 if (state->Mode == 1) /* Digital Mode */ { MXL_VCORange_Test()
1671 MXL5005_TunerConfig(struct dvb_frontend *fe, u8 Mode, u8 IF_mode, u32 Bandwidth, u32 IF_out, u32 Fxtal, u8 AGC_Mode, u16 TOP, u16 IF_OUT_LOAD, u8 CLOCK_OUT, u8 DIV_OUT, u8 CAPSELECT, u8 EN_RSSI, u8 Mod_Type, u8 TF_Type ) MXL5005_TunerConfig() argument
H A Dmt2063.c982 * Mode 0 : | MT2063_CABLE_QAM
983 * Mode 1 : | MT2063_CABLE_ANALOG
984 * Mode 2 : | MT2063_OFFAIR_COFDM
985 * Mode 3 : | MT2063_OFFAIR_COFDM_SAWLESS
986 * Mode 4 : | MT2063_OFFAIR_ANALOG
987 * Mode 5 : | MT2063_OFFAIR_8VSB
990 * |<---------- Mode -------------->|
1198 * @Mode: desired receiver delivery system
1204 enum mt2063_delivery_sys Mode) MT2063_SetReceiverMode()
1212 if (Mode >= MT2063_NUM_RCVR_MODES) MT2063_SetReceiverMode()
1219 reg[MT2063_REG_PD1_TGT] & ~0x40) | (RFAGCEN[Mode] MT2063_SetReceiverMode()
1229 (LNARIN[Mode] & 0x03); MT2063_SetReceiverMode()
1239 (FIFFQEN[Mode] << 7) | (FIFFQ[Mode] << 4); MT2063_SetReceiverMode()
1263 (ACLNAMAX[Mode] & 0x1F); MT2063_SetReceiverMode()
1271 (LNATGT[Mode] & 0x3F); MT2063_SetReceiverMode()
1279 (ACRFMAX[Mode] & 0x1F); MT2063_SetReceiverMode()
1287 (PD1TGT[Mode] & 0x3F); MT2063_SetReceiverMode()
1294 u8 val = ACFIFMAX[Mode]; MT2063_SetReceiverMode()
1306 (PD2TGT[Mode] & 0x3F); MT2063_SetReceiverMode()
1314 (RFOVDIS[Mode] ? 0x80 : 0x00); MT2063_SetReceiverMode()
1322 (FIFOVDIS[Mode] ? 0x80 : 0x00); MT2063_SetReceiverMode()
1328 state->rcvr_mode = Mode; MT2063_SetReceiverMode()
1203 MT2063_SetReceiverMode(struct mt2063_state *state, enum mt2063_delivery_sys Mode) MT2063_SetReceiverMode() argument
/linux-4.4.14/drivers/net/ethernet/amd/
H A Dariadne.h75 #define CSR15 0x0f00 /* - Mode Register */
164 #define ISACSR0 0x0000 /* Master Mode Read Active */
165 #define ISACSR1 0x0100 /* Master Mode Write Active */
219 #define ENTST 0x0080 /* Enable Test Mode */
236 * Bit definitions for CSR15 (Mode Register)
241 #define PROM 0x0080 /* Promiscuous Mode */
246 #define MENDECL 0x0004 /* MENDEC Loopback Mode */
247 #define LRTTSEL 0x0002 /* Low Receive Threshold/Transmit Mode Select */
H A Dni65.h38 * Initialization Block Mode operation Bit Definitions.
41 #define M_PROM 0x8000 /* Promiscuous Mode */
H A Da2065.h90 * Mode Flags
93 #define LE_MO_PROM 0x8000 /* Promiscuous Mode */
/linux-4.4.14/drivers/atm/
H A Didt77105.h33 #define IDT77105_MCR_UMODE 0x02 /* R/W, Utopia (cell/byte) Mode */
52 #define IDT77105_DIAG_UMODE 0x02 /* R/W, Utopia (cell/byte) Mode */
H A DuPD98401.h96 #define uPD98401_GMR 0x00 /* General Mode Register */
129 #define uPD98401_GMR_PM 0x00000020 /* Bus Parity Mode (0 byte, 1 word)*/
132 #define uPD98401_GMR_DR 0x00000004 /* Receive Drop Mode (0drop,1don't)*/
196 #define uPD98401_VRR_SDM 0x80000000 /* Shutdown Mode */
/linux-4.4.14/arch/powerpc/include/asm/
H A Dmpc5121.h18 u32 rmr; /* Reset Mode Register */
28 u32 spmr; /* System PLL Mode Register */
H A Dfsl_lbc.h108 __be32 mamr; /**< UPMA Mode Register */
114 __be32 mbmr; /**< UPMB Mode Register */
115 __be32 mcmr; /**< UPMC Mode Register */
121 __be32 lsdmr; /**< SDRAM Mode Register */
178 __be32 fmr; /**< Flash Mode Register */
H A Dreg_booke.h29 #define MSR_CM_LG 31 /* Computation Mode (0=32-bit, 1=64-bit) */
378 #define DBCR0_EDM 0x80000000 /* External Debug Mode */
379 #define DBCR0_IDM 0x40000000 /* Internal Debug Mode */
411 #define DBCR_IAC12MODE (DBCR0_IA12 | DBCR0_IA12X) /* IAC 1-2 Mode Bits */
414 #define DBCR_IAC34MODE (DBCR0_IA34 | DBCR0_IA34X) /* IAC 3-4 Mode Bits */
440 #define DBCR0_EDM 0x80000000 /* External Debug Mode */
441 #define DBCR0_IDM 0x40000000 /* Internal Debug Mode */
505 #define DBCR_IAC12MODE DBCR1_IAC12MX /* IAC 1-2 Mode Bits */
508 #define DBCR_IAC34MODE DBCR1_IAC34MX /* IAC 3-4 Mode Bits */
518 #define DBCR2_DAC12MODE 0x00C00000 /* DAC 1-2 Mode Bits */
520 #define DBCR2_DVC1M 0x000C0000 /* Data Value Comp 1 Mode */
522 #define DBCR2_DVC2M 0x00030000 /* Data Value Comp 2 Mode */
626 #define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */
H A Dhydra.h69 #define HYDRA_FC_MPIC_IS_MASTER 0x00000100 /* OpenPIC Master Mode */
/linux-4.4.14/arch/mips/include/asm/sibyte/
H A Dsb1250_syncser.h39 * Serial Mode Configuration Register
55 * Serial Clock Source and Line Interface Mode Register
/linux-4.4.14/arch/sh/boards/
H A Dboard-apsh4a3a.c157 value &= ~MODE_PIN0; /* Clock Mode 16 */ apsh4a3a_mode_pins()
166 value |= MODE_PIN9; /* Master Mode */ apsh4a3a_mode_pins()
H A Dboard-apsh4ad0a.c82 value |= MODE_PIN0; /* Clock Mode 3 */ apsh4ad0a_mode_pins()
/linux-4.4.14/drivers/gpio/
H A Dgpio-rcar.c111 * "Setting Edge-Sensitive Interrupt Input Mode" and gpio_rcar_config_interrupt_input_mode()
112 * "Setting Level-Sensitive Interrupt Input Mode" gpio_rcar_config_interrupt_input_mode()
127 /* Select "Interrupt Input Mode" in IOINTSEL */ gpio_rcar_config_interrupt_input_mode()
234 * "Setting General Output Mode" and gpio_rcar_config_general_input_output_mode()
235 * "Setting General Input Mode" gpio_rcar_config_general_input_output_mode()
243 /* Select "General Input/Output Mode" in IOINTSEL */ gpio_rcar_config_general_input_output_mode()
246 /* Select Input Mode or Output Mode in INOUTSEL */ gpio_rcar_config_general_input_output_mode()
/linux-4.4.14/drivers/net/ethernet/dec/tulip/
H A Dde4x5.h16 #define DE4X5_BMR iobase+(0x000 << lp->bus) /* Bus Mode Register */
22 #define DE4X5_OMR iobase+(0x030 << lp->bus) /* Operation Mode Register */
82 #define ER1_IAM 0xe0 /* ISA Address Mode */
203 #define SLEEP 0x80 /* Power Saving Sleep Mode */
204 #define SNOOZE 0x40 /* Power Saving Snooze Mode */
211 ** DC21040 Bus Mode Register (DE4X5_BMR)
331 ** Operation Mode Register (DE4X5_OMR)
336 #define OMR_SCR 0x01000000 /* Scrambler Mode */
338 #define OMR_TTM 0x00400000 /* Transmit Threshold Mode */
346 #define OMR_FC 0x00001000 /* Force Collision Mode */
347 #define OMR_OM 0x00000c00 /* Operating Mode */
348 #define OMR_FDX 0x00000200 /* Full Duplex Mode */
351 #define OMR_PR 0x00000040 /* Promiscuous Mode */
355 #define OMR_HO 0x00000004 /* Hash Only Filtering Mode */
357 #define OMR_HP 0x00000001 /* Hash/Perfect Receive Filtering Mode */
426 #define MII_MDO 0x00060000 /* MII Management Mode/Data Out */
427 #define MII_MRD 0x00040000 /* MII Management Define Read Mode */
428 #define MII_MWR 0x00000000 /* MII Management Define Write Mode */
474 #define MII_CR_ISOL 0x0400 /* Isolate Mode */
476 #define MII_CR_FDM 0x0100 /* Full Duplex Mode */
674 #define SICR_SDM 0xffff0000 /* SIA Diagnostics Mode */
679 #define SICR_EXT 0x00000000 /* SIA MUX Select External SIA Mode */
731 #define SIGR_MD 0x000f0000 /* General Purpose Mode and Data */
/linux-4.4.14/drivers/staging/rtl8188eu/hal/
H A Drtl8188e_cmd.c167 void rtl8188e_set_FwPwrMode_cmd(struct adapter *adapt, u8 Mode) rtl8188e_set_FwPwrMode_cmd() argument
173 DBG_88E("%s: Mode=%d SmartPS=%d UAPSD=%d\n", __func__, rtl8188e_set_FwPwrMode_cmd()
174 Mode, pwrpriv->smart_ps, adapt->registrypriv.uapsd_enable); rtl8188e_set_FwPwrMode_cmd()
176 switch (Mode) { rtl8188e_set_FwPwrMode_cmd()
178 H2CSetPwrMode.Mode = 0; rtl8188e_set_FwPwrMode_cmd()
181 H2CSetPwrMode.Mode = 1; rtl8188e_set_FwPwrMode_cmd()
185 H2CSetPwrMode.Mode = 1; rtl8188e_set_FwPwrMode_cmd()
189 H2CSetPwrMode.Mode = 1; rtl8188e_set_FwPwrMode_cmd()
192 H2CSetPwrMode.Mode = 2; rtl8188e_set_FwPwrMode_cmd()
195 H2CSetPwrMode.Mode = 0; rtl8188e_set_FwPwrMode_cmd()
205 if (Mode > 0) rtl8188e_set_FwPwrMode_cmd()
/linux-4.4.14/drivers/staging/iio/adc/
H A Dad7192.c33 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
59 /* Mode Register Bit Designations (AD7192_REG_MODE) */
60 #define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */
61 #define AD7192_MODE_SEL_MASK (0x7 << 21) /* Operation Mode Select Mask */
72 /* Mode Register: AD7192_MODE_SEL options */
73 #define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */
74 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */
75 #define AD7192_MODE_IDLE 2 /* Idle Mode */
76 #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */
82 /* Mode Register: AD7192_MODE_CLKSRC options */
99 #define AD7192_CONF_BUF BIT(4) /* Buffered Mode Enable */
/linux-4.4.14/arch/blackfin/mach-bf533/include/mach/
H A Danomaly.h74 /* Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode */
80 /* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */
96 /* SPI Slave Boot Mode Modifies Registers from Reset Value */
114 /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
118 /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
188 /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
192 /* PPI Does Not Start Properly In Specific Mode */
242 /* Timer Auto-Baud Mode requires the UART clock to be enabled. */
278 /* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
316 /* Frame Delay in SPORT Multichannel Mode */
340 /* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */
/linux-4.4.14/drivers/scsi/
H A Dnsp32_debug.c19 /* 13-16 */ unknown, "Recover Buffered Data", "Mode Select", "Reserve",
20 /* 17-1b */ "Release", "Copy", "Erase", "Mode Sense", "Start/Stop Unit",
42 /* 50-55 */ unknown, unknown, unknown, unknown, unknown, "Mode Select (10)",
43 /* 56-5b */ unknown, unknown, unknown, unknown, "Mode Sense (10)", unknown,
H A Dhpsa_cmd.h300 u8 Mode:2; /* b00 */ member in struct:SCSI3Addr::__anon9487
305 u8 Mode:2; /* b01 */ member in struct:SCSI3Addr::__anon9488
311 u8 Mode:2; /* b10 */ member in struct:SCSI3Addr::__anon9489
318 u32 Mode:2; member in struct:PhysDevAddr
325 u32 Mode:2; member in struct:LogDevAddr
517 * SCSI Response Format structure for IO Accelerator Mode 2
590 * defines for Mode 2 command struct
600 * SCSI Task Management Request format for Accelerator Mode 2
/linux-4.4.14/drivers/spi/
H A Dspi-fsl-spi.h58 * Default for SPI Mode:
/linux-4.4.14/drivers/isdn/hardware/eicon/
H A Ddqueue.c4 * User Mode IDI Interface
/linux-4.4.14/drivers/mmc/host/
H A Datmel-mci-regs.h26 #define ATMCI_MR 0x0004 /* Mode */
33 # define ATMCI_MR_PDCMODE ( 1 << 15) /* PDC-oriented Mode */
123 # define ATMCI_CFG_HSMODE ( 1 << 8) /* High Speed Mode */
125 #define ATMCI_WPMR 0x00e4 /* Write Protection Mode[2] */
/linux-4.4.14/drivers/net/ethernet/intel/e1000e/
H A D82571.h42 /* Manageability Operation Mode mask */
H A D80003es2lan.h75 /* Kumeran Mode Control Register (Page 193, Register 16) */
H A Dich8lan.h145 #define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */
146 #define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */
149 #define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */
215 /* KMRN Mode Control */
/linux-4.4.14/drivers/net/wan/
H A Dhd64570.h59 #define MD0 0x0E /* Mode 0 */
60 #define MD1 0x0F /* Mode 1 */
61 #define MD2 0x10 /* Mode 2 */
132 #define DMR 0x11 /* DMA Mode */
/linux-4.4.14/arch/x86/include/asm/
H A Dsmap.h2 * Supervisor Mode Access Prevention support
/linux-4.4.14/include/linux/power/
H A Dmax8903_charger.h38 int dcm; /* Current-Limit Mode input (1: DC, 2: USB) */
/linux-4.4.14/arch/mips/lantiq/falcon/
H A Dreset.c22 /* CPU0 Boot Mode Register */
/linux-4.4.14/arch/avr32/mach-at32ap/
H A Dsdramc.h23 /* MR - Mode Register */
/linux-4.4.14/arch/arm/mach-shmobile/
H A Dheadsmp-scu.S36 bic r2, r2, r3 @ Clear bits of our CPU (Run Mode)
/linux-4.4.14/arch/arm/boot/dts/
H A Dst-pincfg.h42 * B Mode
/linux-4.4.14/drivers/video/fbdev/via/
H A Dviamode.c56 /* Video Mode Table for VT3314 chipset*/
57 /* Common Setting for Video Mode */
144 /* For VT3324: Common Setting for Video Mode */
212 /* Video Mode Table */
213 /* Common Setting for Video Mode */
237 /* Mode:1024X768 */
268 /* Mode Table */
/linux-4.4.14/include/linux/rtc/
H A Dds1685.h109 * Bit masks for the Time registers in BCD Mode (DM = 0).
120 * Bit masks for the Time registers in BIN Mode (DM = 1).
131 * Bit masks common for the Time registers in BCD or BIN Mode.
172 #define RTC_CTRL_B_DM BIT(2) /* Data Mode */
173 #define RTC_CTRL_B_2412 BIT(1) /* 12-Hr/24-Hr Mode */
207 * On the DS17x85/DS17x87, BIT(5) is Burst-Mode Enable (BME), and allows
218 #define RTC_CTRL_4A_BME BIT(5) /* Burst-Mode Enable */
/linux-4.4.14/drivers/tty/serial/
H A Dip22zilog.h90 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
92 #define ENT_HM 0x10 /* Enter Hunt Mode */
112 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
113 #define EXTSYNC 0x30 /* External Sync Mode */
164 /* Write Register 11 (Clock Mode control) */
H A Dsunzilog.h82 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
84 #define ENT_HM 0x10 /* Enter Hunt Mode */
104 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
105 #define EXTSYNC 0x30 /* External Sync Mode */
166 /* Write Register 11 (Clock Mode control) */
H A Dzs.h109 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
111 #define ENT_HM 0x10 /* Enter Hunt Mode */
131 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
132 #define EXTSYNC 0x30 /* External Sync Mode */
183 /* Write Register 11 (Clock Mode Control) */
H A Dm32r_sio_reg.h58 #define UART_EMSR 0 /* (LCR=BF) Extended Mode Select Register
97 #define UART_EMSR 0 /* (LCR=BF) Extended Mode Select Register
H A Dsh-sci.h15 SCSMR, /* Serial Mode Register */
35 /* SCSMR (Serial Mode Register) */
/linux-4.4.14/drivers/media/pci/ttpci/
H A Dav7110_hw.h44 #define SB_OFF SAA7146_GPIO_OUTLO /* SlowBlank off (TV-Mode) */
45 #define SB_ON SAA7146_GPIO_INPUT /* SlowBlank on (AV-Mode) */
46 #define SB_WIDE SAA7146_GPIO_OUTHI /* SlowBlank 6V (16/9-Mode) (not implemented) */
49 #define FB_OFF SAA7146_GPIO_LO /* FastBlank off (CVBS-Mode) */
50 #define FB_ON SAA7146_GPIO_OUTHI /* FastBlank on (RGB-Mode) */
/linux-4.4.14/drivers/iio/adc/
H A Dad7793.c33 #define AD7793_REG_MODE 1 /* Mode Register (RW, 16-bit */
57 /* Mode Register Bit Designations (AD7793_REG_MODE) */
58 #define AD7793_MODE_SEL(x) (((x) & 0x7) << 13) /* Operation Mode Select */
59 #define AD7793_MODE_SEL_MASK (0x7 << 13) /* Operation Mode Select mask */
63 #define AD7793_MODE_CONT 0 /* Continuous Conversion Mode */
64 #define AD7793_MODE_SINGLE 1 /* Single Conversion Mode */
65 #define AD7793_MODE_IDLE 2 /* Idle Mode */
66 #define AD7793_MODE_PWRDN 3 /* Power-Down Mode */
87 #define AD7793_CONF_BUF (1 << 4) /* Buffered Mode Enable */
/linux-4.4.14/drivers/dma/
H A Dat_hdmac_regs.h144 #define ATC_SRC_ADDR_MODE_INCR (0x0 << 24) /* Incrementing Mode */
145 #define ATC_SRC_ADDR_MODE_DECR (0x1 << 24) /* Decrementing Mode */
146 #define ATC_SRC_ADDR_MODE_FIXED (0x2 << 24) /* Fixed Mode */
148 #define ATC_DST_ADDR_MODE_INCR (0x0 << 28) /* Incrementing Mode */
149 #define ATC_DST_ADDR_MODE_DECR (0x1 << 28) /* Decrementing Mode */
150 #define ATC_DST_ADDR_MODE_FIXED (0x2 << 28) /* Fixed Mode */
/linux-4.4.14/arch/blackfin/mach-bf527/include/mach/
H A Danomaly.h48 /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
82 /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
92 /* 8-Bit NAND Flash Boot Mode Not Functional */
154 /* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */
190 /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
194 /* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
H A DdefBF527.h15 #define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
170 #define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
171 #define PR 0x00000080 /* Promiscuous Mode Enable */
176 #define RAF 0x00001000 /* Receive-All Mode */
188 #define RMII 0x01000000 /* RMII/MII* Mode */
190 #define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
192 #define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
336 #define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
/linux-4.4.14/drivers/isdn/act2000/
H A Dact2000_isa.h94 /* IMS C011 Mode 2 Input Status Register for INMOS CPU SIS (RW) */
104 /* IMS C011 Mode 2 Output Status Register from INMOS CPU SOS (RW) */
/linux-4.4.14/drivers/iio/humidity/
H A Dsi7020.c37 /* Measure Relative Humidity, Hold Master Mode */
39 /* Measure Temperature, Hold Master Mode */
/linux-4.4.14/drivers/media/usb/gspca/stv06xx/
H A Dstv06xx_pb0100.h47 #define PB_CONTROL 0x07 /* Control Mode */
72 #define PB_PREADCTRL 0x20 /* Pixel Read Control Mode */
/linux-4.4.14/drivers/media/dvb-frontends/
H A Dm88ds3103.h54 #define M88DS3103_TS_CI 3 /* TS CI Mode */
108 #define M88DS3103_TS_CI 3 /* TS CI Mode */
/linux-4.4.14/drivers/net/phy/
H A Dicplus.c42 #define IP1001_APS_ON 11 /* IP1001 APS Mode bit */
43 #define IP101A_G_APS_ON 2 /* IP101A/G APS Mode bit */
/linux-4.4.14/drivers/net/ethernet/oki-semi/pch_gbe/
H A Dpch_gbe.h120 /* Mode */
121 #define PCH_GBE_MODE_MII_ETHER 0x00000000 /* GIGA Ethernet Mode [MII] */
122 #define PCH_GBE_MODE_GMII_ETHER 0x80000000 /* GIGA Ethernet Mode [GMII] */
123 #define PCH_GBE_MODE_HALF_DUPLEX 0x00000000 /* Duplex Mode [half duplex] */
124 #define PCH_GBE_MODE_FULL_DUPLEX 0x40000000 /* Duplex Mode [full duplex] */
147 /* RX Mode */
213 /* TX Mode */
358 * @fc: Mode of flow control
/linux-4.4.14/drivers/power/reset/
H A Dat91-poweroff.c24 #define AT91_SHDW_MR 0x04 /* Shut Down Mode Register */
25 #define AT91_SHDW_WKMODE0 GENMASK(2, 0) /* Wake-up 0 Mode Selection */
/linux-4.4.14/arch/blackfin/mach-bf609/include/mach/
H A Danomaly.h65 /* SPORT May Drive Data Pins During Inactive Channels in Multichannel Mode */
69 /* Default SPI Master Boot Mode Setting is Incorrect */
/linux-4.4.14/include/net/
H A Dlapb.h20 #define LAPB_SABM 0x2F /* Set Asynchronous Balanced Mode */
21 #define LAPB_SABME 0x6F /* Set Asynchronous Balanced Mode Extended */
/linux-4.4.14/arch/s390/include/asm/
H A Dptrace.h30 unsigned long long t : 1; /* DAT Mode */
43 unsigned long long eaba : 2; /* Addressing Mode */
/linux-4.4.14/arch/blackfin/mach-bf518/include/mach/
H A DdefBF516.h16 #define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
171 #define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
172 #define PR 0x00000080 /* Promiscuous Mode Enable */
177 #define RAF 0x00001000 /* Receive-All Mode */
189 #define RMII 0x01000000 /* RMII/MII* Mode */
191 #define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
193 #define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
337 #define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
/linux-4.4.14/include/linux/i2c/
H A Dbfin_twi.h97 #define MEN 0x0001 /* Master Mode Enable */
100 #define FAST 0x0008 /* Use Fast Mode Timing Specs */
/linux-4.4.14/drivers/vfio/platform/reset/
H A Dvfio_platform_calxedaxgmac.c37 #define XGMAC_DMA_CONTROL 0x00000f18 /* Ctrl (Operational Mode) */
/linux-4.4.14/drivers/video/backlight/
H A Dltv350qv.h19 #define LTV_ENTRY_MODE 0x03 /* Entry Mode */
/linux-4.4.14/drivers/media/pci/ivtv/
H A Divtv-gpio.c43 * AM* : Audio Mode
49 * DM* : Detected tuner audio Mode
77 * AM* : Audio Mode
91 * DM* : Detected tuner audio Mode
/linux-4.4.14/drivers/media/usb/gspca/
H A Dse401.h50 /* Mode registers: */
/linux-4.4.14/arch/arc/include/asm/
H A Dirqflags-arcv2.h31 /* Was Intr taken in User Mode */
/linux-4.4.14/fs/ntfs/
H A Dsysctl.c42 .mode = 0644, /* Mode, proc handler. */
/linux-4.4.14/arch/mips/kernel/
H A Dsegment.c51 seq_puts(m, "Segment Virtual Size Access Mode Physical Caching EU\n"); show_segments()
/linux-4.4.14/arch/sh/boards/mach-rsk/
H A Ddevices-rsk7203.c133 /* Setup LAN9118: CS1 in 16-bit Big Endian Mode, IRQ0 at Port B */ rsk7203_devices_setup()
/linux-4.4.14/arch/sh/include/mach-common/mach/
H A Dsdk7780.h62 #define FPGA_PCIMR (PA_FPGA + 0x140) /* PCI Mode */

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