/linux-4.4.14/arch/sh/kernel/cpu/sh4a/ |
H A D | clock-sh7757.c | 79 #define MSTPCR1 0xffc80034 macro 91 /* MSTPCR1 */ 92 [MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 27, 0), 93 [MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0), 94 [MSTP113] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 13, 0), 95 [MSTP112] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 12, 0), 96 [MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0), 97 [MSTP110] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 10, 0), 98 [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0), 99 [MSTP102] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 2, 0),
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H A D | clock-sh7786.c | 83 #define MSTPCR1 0xffc40034 macro 117 /* MSTPCR1 */ 118 [MSTP112] = SH_CLK_MSTP32(NULL, MSTPCR1, 12, 0), 119 [MSTP110] = SH_CLK_MSTP32(NULL, MSTPCR1, 10, 0), 120 [MSTP109] = SH_CLK_MSTP32(NULL, MSTPCR1, 9, 0), 121 [MSTP108] = SH_CLK_MSTP32(NULL, MSTPCR1, 8, 0), 122 [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0), 123 [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0), 124 [MSTP103] = SH_CLK_MSTP32(NULL, MSTPCR1, 3, 0), 125 [MSTP102] = SH_CLK_MSTP32(NULL, MSTPCR1, 2, 0),
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H A D | clock-shx3.c | 77 #define MSTPCR1 0xffc00034 macro 97 /* MSTPCR1 */ 98 [MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0), 99 [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0), 100 [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
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H A D | clock-sh7734.c | 85 #define MSTPCR1 0xFFC80034 macro 148 /* MSTPCR1 */ 149 [MSTP115] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 15, 0), 150 [MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0), 151 [MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0), 152 [MSTP109] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0), 153 [MSTP108] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 8, 0), 154 [MSTP107] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 7, 0), 155 [MSTP106] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 6, 0), 156 [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0), 157 [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0),
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H A D | clock-sh7785.c | 84 #define MSTPCR1 0xffc80034 macro 111 /* MSTPCR1 */ 112 [MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0), 113 [MSTP117] = SH_CLK_MSTP32(NULL, MSTPCR1, 17, 0), 114 [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0), 115 [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0), 116 [MSTP100] = SH_CLK_MSTP32(NULL, MSTPCR1, 0, 0),
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H A D | clock-sh7724.c | 39 #define MSTPCR1 0xa4150034 macro 241 [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 12, 0), 242 [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 11, 0), 243 [HWBLK_IIC0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0), 244 [HWBLK_IIC1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
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H A D | clock-sh7343.c | 34 #define MSTPCR1 0xa4150034 macro 175 [MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0), 176 [MSTP108] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
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H A D | clock-sh7722.c | 37 #define MSTPCR1 0xa4150034 macro 164 [HWBLK_IIC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0), 165 [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 8, 0),
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H A D | clock-sh7723.c | 38 #define MSTPCR1 0xa4150034 macro 182 [HWBLK_IIC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0), 183 [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 8, 0),
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H A D | clock-sh7366.c | 34 #define MSTPCR1 0xa4150034 macro 176 [MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
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/linux-4.4.14/arch/sh/include/cpu-sh4/cpu/ |
H A D | freq.h | 23 #define MSTPCR1 0xa4150034 macro 47 #define MSTPCR1 0xa4150034 macro
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/linux-4.4.14/arch/sh/include/mach-common/mach/ |
H A D | sh7763rdp.h | 18 #define MSTPCR1 0xFFC80038 macro
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/linux-4.4.14/arch/sh/boards/mach-sh7763rdp/ |
H A D | setup.c | 208 __raw_writel(__raw_readl(MSTPCR1) & ~0x8, MSTPCR1); sh7763rdp_setup()
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