| /linux-4.4.14/arch/arm/mach-imx/ |
| H A D | pm-imx27.c | 21 /* Clear MPEN and SPEN to disable MPLL/SPLL */ mx27_suspend_enter()
|
| /linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/clock/ |
| H A D | s3c2410.h | 25 #define MPLL 2 macro
|
| H A D | s3c2412.h | 25 #define MPLL 2 macro
|
| /linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/clock/ |
| H A D | s3c2410.h | 25 #define MPLL 2 macro
|
| H A D | s3c2412.h | 25 #define MPLL 2 macro
|
| /linux-4.4.14/include/dt-bindings/clock/ |
| H A D | s3c2410.h | 25 #define MPLL 2 macro
|
| H A D | s3c2412.h | 25 #define MPLL 2 macro
|
| /linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/clock/ |
| H A D | s3c2410.h | 25 #define MPLL 2 macro
|
| H A D | s3c2412.h | 25 #define MPLL 2 macro
|
| /linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/clock/ |
| H A D | s3c2410.h | 25 #define MPLL 2 macro
|
| H A D | s3c2412.h | 25 #define MPLL 2 macro
|
| /linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/clock/ |
| H A D | s3c2410.h | 25 #define MPLL 2 macro
|
| H A D | s3c2412.h | 25 #define MPLL 2 macro
|
| /linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/clock/ |
| H A D | s3c2410.h | 25 #define MPLL 2 macro
|
| H A D | s3c2412.h | 25 #define MPLL 2 macro
|
| /linux-4.4.14/drivers/clk/samsung/ |
| H A D | clk-s3c2410.c | 151 ALIAS(MPLL, NULL, "mpll"),
197 [mpll] = PLL(pll_s3c2410_mpll, MPLL, "mpll", "xti",
263 [mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti",
|
| H A D | clk-s3c2412.c | 147 [mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti",
203 ALIAS(MPLL, NULL, "mpll"),
|
| H A D | clk-exynos3250.c | 656 /* APLL & MPLL & BPLL & UPLL */
|
| H A D | clk-exynos4415.c | 860 * APLL & MPLL & BPLL & ISP_PLL & DISP_PLL & G3D_PLL
|
| /linux-4.4.14/sound/soc/samsung/ |
| H A D | s3c2412-i2s.c | 72 /* Set MPLL as the source for IIS CLK */ s3c2412_i2s_probe()
|
| /linux-4.4.14/drivers/cpufreq/ |
| H A D | s5pv210-cpufreq.c | 293 * APLL -> MPLL(for stable transition) -> APLL s5pv210_target()
428 /* 9. Change MPLL to APLL in MSYS_MUX */ s5pv210_target()
|
| /linux-4.4.14/drivers/clk/ingenic/ |
| H A D | jz4780-cgu.c | 255 .pll = DEF_PLL(MPLL),
|
| /linux-4.4.14/arch/arm/plat-samsung/include/plat/ |
| H A D | cpu-freq-core.h | 136 * @locktime_m: The lock-time in uS for the MPLL.
|
| /linux-4.4.14/drivers/video/fbdev/aty/ |
| H A D | radeon_pm.c | 1514 /* Reconfigure MPLL charge pump, VCO gain, duty cycle */ radeon_pm_start_mclk_sclk()
1521 /* Set MPLL feedback divider */ radeon_pm_start_mclk_sclk()
1526 /* Power up MPLL */ radeon_pm_start_mclk_sclk()
1533 /* Un-reset MPLL */ radeon_pm_start_mclk_sclk()
|
| /linux-4.4.14/drivers/gpu/drm/nouveau/dispnv04/ |
| H A D | hw.c | 145 /* single stage NVPLL and VPLLs use 1 << 8, MPLL uses 1 << 12 */ nouveau_hw_decode_pll()
|
| /linux-4.4.14/drivers/gpu/drm/bridge/ |
| H A D | dw_hdmi.c | 760 /* PLL/MPLL Cfg - always match on final entry */ hdmi_phy_configure()
|
| /linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
| H A D | init.c | 1576 /* MPLL */ init_configure_clk()
|
| /linux-4.4.14/drivers/gpu/drm/radeon/ |
| H A D | atombios.h | 432 #define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
439 #define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
|
| /linux-4.4.14/drivers/gpu/drm/amd/include/ |
| H A D | atombios.h | 419 #define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
426 #define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
|