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Searched refs:MLXSW_ITEM32 (Results 1 – 7 of 7) sorted by relevance

/linux-4.4.14/drivers/net/ethernet/mellanox/mlxsw/
Dcmd.h234 MLXSW_ITEM32(cmd_mbox, query_fw, fw_pages, 0x00, 16, 16);
239 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_major, 0x00, 0, 16);
244 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_subminor, 0x04, 16, 16);
249 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_minor, 0x04, 0, 16);
254 MLXSW_ITEM32(cmd_mbox, query_fw, core_clk, 0x08, 16, 16);
261 MLXSW_ITEM32(cmd_mbox, query_fw, cmd_interface_rev, 0x08, 0, 16);
266 MLXSW_ITEM32(cmd_mbox, query_fw, dt, 0x0C, 31, 1);
272 MLXSW_ITEM32(cmd_mbox, query_fw, api_version, 0x0C, 0, 16);
277 MLXSW_ITEM32(cmd_mbox, query_fw, fw_hour, 0x10, 24, 8);
282 MLXSW_ITEM32(cmd_mbox, query_fw, fw_minutes, 0x10, 16, 8);
[all …]
Dpci.h97 MLXSW_ITEM32(pci, wqe, c, 0x00, 31, 1);
109 MLXSW_ITEM32(pci, wqe, lp, 0x00, 30, 1);
114 MLXSW_ITEM32(pci, wqe, type, 0x00, 23, 4);
130 MLXSW_ITEM32(pci, cqe, lag, 0x00, 23, 1);
138 MLXSW_ITEM32(pci, cqe, system_port, 0x00, 0, 16);
143 MLXSW_ITEM32(pci, cqe, wqe_counter, 0x04, 16, 16);
150 MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14);
155 MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 8);
161 MLXSW_ITEM32(pci, cqe, crc, 0x0C, 8, 1);
166 MLXSW_ITEM32(pci, cqe, e, 0x0C, 7, 1);
[all …]
Dreg.h74 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
124 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
131 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
139 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
149 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
177 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
186 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
218 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
252 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
261 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
[all …]
Dcore.c144 MLXSW_ITEM32(emad, eth_hdr, ethertype, 0x0C, 16, 16);
150 MLXSW_ITEM32(emad, eth_hdr, mlx_proto, 0x0C, 8, 8);
156 MLXSW_ITEM32(emad, eth_hdr, ver, 0x0C, 4, 4);
162 MLXSW_ITEM32(emad, op_tlv, type, 0x00, 27, 5);
168 MLXSW_ITEM32(emad, op_tlv, len, 0x00, 16, 11);
176 MLXSW_ITEM32(emad, op_tlv, dr, 0x00, 15, 1);
193 MLXSW_ITEM32(emad, op_tlv, status, 0x00, 8, 7);
198 MLXSW_ITEM32(emad, op_tlv, register_id, 0x04, 16, 16);
203 MLXSW_ITEM32(emad, op_tlv, r, 0x04, 15, 1);
212 MLXSW_ITEM32(emad, op_tlv, method, 0x04, 8, 7);
[all …]
Dswitchx2.c87 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
94 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
99 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
106 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 18, 3);
111 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
121 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
126 MLXSW_ITEM32(tx, hdr, ctclass3, 0x04, 14, 1);
132 MLXSW_ITEM32(tx, hdr, rdq, 0x04, 9, 5);
137 MLXSW_ITEM32(tx, hdr, cpu_sig, 0x04, 0, 9);
142 MLXSW_ITEM32(tx, hdr, sig, 0x0C, 16, 16);
[all …]
Dspectrum.c68 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
75 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
80 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
85 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
91 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
96 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
102 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
107 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
117 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
124 MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
[all …]
Ditem.h291 #define MLXSW_ITEM32(_type, _cname, _iname, _offset, _shift, _sizebits) \ macro