Searched refs:MIC_X100_SBOX_BASE_ADDRESS (Results 1 - 4 of 4) sorted by relevance

/linux-4.4.14/drivers/misc/mic/host/
H A Dmic_x100.c49 MIC_X100_SBOX_BASE_ADDRESS + mic_x100_write_spad()
66 MIC_X100_SBOX_BASE_ADDRESS + mic_x100_read_spad()
82 u32 sice0 = MIC_X100_SBOX_BASE_ADDRESS + MIC_X100_SBOX_SICE0; mic_x100_enable_interrupts()
83 u32 siac0 = MIC_X100_SBOX_BASE_ADDRESS + MIC_X100_SBOX_SIAC0; mic_x100_enable_interrupts()
109 u32 sice0 = MIC_X100_SBOX_BASE_ADDRESS + MIC_X100_SBOX_SICE0; mic_x100_disable_interrupts()
110 u32 siac0 = MIC_X100_SBOX_BASE_ADDRESS + MIC_X100_SBOX_SIAC0; mic_x100_disable_interrupts()
111 u32 sicc0 = MIC_X100_SBOX_BASE_ADDRESS + MIC_X100_SBOX_SICC0; mic_x100_disable_interrupts()
133 u32 apicicr_low = mic_mmio_read(mw, MIC_X100_SBOX_BASE_ADDRESS + mic_x100_send_sbox_intr()
142 MIC_X100_SBOX_BASE_ADDRESS + apic_icr_offset); mic_x100_send_sbox_intr()
156 MIC_X100_SBOX_BASE_ADDRESS + rdmasr_offset); mic_x100_send_rdmasr_intr()
184 u32 sicr0 = MIC_X100_SBOX_BASE_ADDRESS + MIC_X100_SBOX_SICR0; mic_x100_ack_interrupt()
203 mic_mmio_write(mw, 1, MIC_X100_SBOX_BASE_ADDRESS + mic_x100_intr_workarounds()
233 MIC_X100_SBOX_BASE_ADDRESS + mic_x100_read_msi_to_src_map()
253 u32 mxar = MIC_X100_SBOX_BASE_ADDRESS + mic_x100_program_msi_to_src_map()
313 MIC_X100_SBOX_BASE_ADDRESS + apic_icr_offset + 4); mic_x100_send_firmware_intr()
318 MIC_X100_SBOX_BASE_ADDRESS + apic_icr_offset); mic_x100_send_firmware_intr()
328 u32 rgcr = MIC_X100_SBOX_BASE_ADDRESS + MIC_X100_SBOX_RGCR; mic_x100_hw_reset()
524 MIC_X100_SBOX_BASE_ADDRESS + mic_x100_smpt_set()
H A Dmic_x100.h43 #define MIC_X100_SBOX_BASE_ADDRESS 0x00010000 macro
/linux-4.4.14/drivers/misc/mic/card/
H A Dmic_x100.c51 MIC_X100_SBOX_BASE_ADDRESS + mic_read_spad()
69 MIC_X100_SBOX_BASE_ADDRESS + mic_send_intr()
79 u32 apicicr_low = mic_mmio_read(mw, MIC_X100_SBOX_BASE_ADDRESS + mic_x100_send_sbox_intr()
92 MIC_X100_SBOX_BASE_ADDRESS + apic_icr_offset); mic_x100_send_sbox_intr()
105 mic_mmio_write(mw, 0, MIC_X100_SBOX_BASE_ADDRESS + rdmasr_offset); mic_x100_send_rdmasr_intr()
H A Dmic_x100.h32 #define MIC_X100_SBOX_BASE_ADDRESS 0x00010000ULL macro

Completed in 126 milliseconds