Searched refs:MFC_STATE1_MASTER_RUN_CONTROL_MASK (Results 1 – 6 of 6) sorted by relevance
245 sr1 = spu_mfc_sr1_get(spu) | MFC_STATE1_MASTER_RUN_CONTROL_MASK; in spu_hw_master_start()256 sr1 = spu_mfc_sr1_get(spu) & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK; in spu_hw_master_stop()
314 sr1 = csa->priv1.mfc_sr1_RW | MFC_STATE1_MASTER_RUN_CONTROL_MASK; in spu_backing_master_start()325 sr1 = csa->priv1.mfc_sr1_RW & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK; in spu_backing_master_stop()
510 spu_mfc_sr1_set(spu, (MFC_STATE1_MASTER_RUN_CONTROL_MASK | in setup_mfc_sr1()1057 MFC_STATE1_MASTER_RUN_CONTROL_MASK); in clear_spu_status()1069 MFC_STATE1_MASTER_RUN_CONTROL_MASK); in clear_spu_status()1898 spu_mfc_sr1_set(spu, MFC_STATE1_MASTER_RUN_CONTROL_MASK); in force_spu_isolate_exit()2164 MFC_STATE1_MASTER_RUN_CONTROL_MASK | in init_priv1()
496 #define MFC_STATE1_MASTER_RUN_CONTROL_MASK 0x20ull macro
718 tmp &= ~MFC_STATE1_MASTER_RUN_CONTROL_MASK; in crash_kexec_stop_spus()
3144 tmp &= ~MFC_STATE1_MASTER_RUN_CONTROL_MASK; in stop_spus()