Searched refs:MCFINT_VECBASE (Results 1 - 11 of 11) sorted by relevance

/linux-4.4.14/arch/m68k/include/asm/
H A Dm54xxsim.h14 #define MCFINT_VECBASE 64 macro
42 #define MCF_IRQ_TIMER (MCFINT_VECBASE + 54) /* Slice Timer 0 */
43 #define MCF_IRQ_PROFILER (MCFINT_VECBASE + 53) /* Slice Timer 1 */
44 #define MCF_IRQ_UART0 (MCFINT_VECBASE + 35)
45 #define MCF_IRQ_UART1 (MCFINT_VECBASE + 34)
46 #define MCF_IRQ_UART2 (MCFINT_VECBASE + 33)
47 #define MCF_IRQ_UART3 (MCFINT_VECBASE + 32)
66 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
H A Dm520xsim.h49 #define MCFINT_VECBASE 64 macro
59 #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
60 #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
61 #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
63 #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
64 #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
65 #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
67 #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
68 #define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
139 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
H A Dm523xsim.h36 #define MCFINT_VECBASE 64 /* Vector base number */ macro
46 #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
47 #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
48 #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
50 #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
51 #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
52 #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
54 #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
55 #define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
187 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
H A Dm528xsim.h36 #define MCFINT_VECBASE 64 /* Vector base number */ macro
46 #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
47 #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
48 #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
50 #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
51 #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
52 #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
54 #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
55 #define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
233 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
H A Dm527xsim.h36 #define MCFINT_VECBASE 64 /* Vector base number */ macro
51 #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
52 #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
53 #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
55 #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
56 #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
57 #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
62 #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
63 #define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
197 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
306 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
H A Dm5441xsim.h30 #define MCFINT_VECBASE 64 macro
31 #define MCFINT0_VECBASE MCFINT_VECBASE
273 #define MCFGPIO_IRQ_VECBASE (MCFINT_VECBASE - MCFGPIO_IRQ_MIN)
H A Dm53xxsim.h18 #define MCFINT_VECBASE 64 macro
27 #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
28 #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
29 #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
31 #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
32 #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
33 #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
35 #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
1101 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
H A Dm5272sim.h97 #define MCFINT_VECBASE 64 /* Base of interrupts */ macro
/linux-4.4.14/arch/m68k/coldfire/
H A Dintc-5272.c44 static struct irqmap intc_irqmap[MCFINT_VECMAX - MCFINT_VECBASE] = {
85 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) { intc_irq_mask()
87 irq -= MCFINT_VECBASE; intc_irq_mask()
97 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) { intc_irq_unmask()
99 irq -= MCFINT_VECBASE; intc_irq_unmask()
110 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) { intc_irq_ack()
111 irq -= MCFINT_VECBASE; intc_irq_ack()
126 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) { intc_irq_set_type()
127 irq -= MCFINT_VECBASE; intc_irq_set_type()
174 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) init_IRQ()
175 edge = intc_irqmap[irq - MCFINT_VECBASE].ack; init_IRQ()
H A Dintc-2.c52 unsigned int irq = d->irq - MCFINT_VECBASE; intc_irq_mask()
70 unsigned int irq = d->irq - MCFINT_VECBASE; intc_irq_unmask()
114 unsigned int irq = d->irq - MCFINT_VECBASE; intc_irq_startup()
203 for (irq = MCFINT_VECBASE; (irq < MCFINT_VECBASE + NR_VECS); irq++) { init_IRQ()
H A Dintc-simr.c69 unsigned int irq = d->irq - MCFINT_VECBASE; intc_irq_mask()
81 unsigned int irq = d->irq - MCFINT_VECBASE; intc_irq_unmask()
117 irq -= MCFINT_VECBASE; intc_irq_startup()
188 eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0) + init_IRQ()
190 for (irq = MCFINT_VECBASE; (irq < eirq); irq++) { init_IRQ()

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