Searched refs:IPI (Results 1 – 20 of 20) sorted by relevance
27 # IPI interrupt handler54 # Cache flush IPI interrupt handler75 # SMP boot CPU IPI interrupt handler
312 bne nmi_not_debugger # if not kernel debugger NMI IPI, jump314 # kernel debugger NMI IPI
52 # Set up the Boot IPI for each secondary CPU
29 * Pending IPI (inter-processor interrupt) priority, 8 bits30 Zero is the highest priority, 255 means no IPI is pending.33 Zero means no interrupt pending, 2 means an IPI is pending
71 non-IPI interrupts to a single CPU at a time (EG: Freescale MPIC).127 2 = MPIC inter-processor interrupt (IPI)130 the MPIC IPI number. The type-specific193 * MPIC IPI interrupts. Note the interrupt
107 ldi r6, #0x2 ; IPI to CPU1164 ;; enable only IPI
351 HAC, IPI, SPDIF, HUDI, I2C, enumerator377 INTC_VECT(HAC, 0x580), INTC_VECT(IPI, 0x5c0),437 DMAC, I2C, HUDI, SPDIF, IPI, HAC, TMU, GPIO } },442 { 0xffe00004, 0, 32, 8, /* INT2PRI1 */ { IPI, SPDIF, HUDI, I2C } },
48 VECTOR handle_interrupt ; (19) Inter core Interrupt (IPI)50 VECTOR handle_interrupt ; (21) Software Triggered Intr (Self IPI)
49 1: Soft-irq. Uses IPI to complete IOs across CPU nodes. Simulates the overhead
81 performs an IPI to inform all processors about the new mapping. This results
137 /* IPI called on each CPU. */
278 unless absolutely necessary. Please consider using an IPI to wake up
110 CPU awakens, the scheduler will send an IPI that can result in
221 ;; SLEEP and wait IPI
156 global clock event devices. The support of such hardware would involve IPI
174 reschedule IPI, that the expedited grace period has been going on for
595 to each of the threads, where the IPI handler will also write
134 packets have been queued to their backlog queue. The IPI wakes backlog
1234 which sends an IPI to the CPUs that are running the same ASID
887 # are unmapped instead of sending one IPI per page to flush. The architecture