Searched refs:INTx (Results 1 – 9 of 9) sorted by relevance
33 The core provides a single interrupt for both INTx/MSI messages. So,36 the four INTx interrupts in ISR and route them to this domain.
22 …tus: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
1334 If KVM_DEV_ASSIGN_PCI_2_3 is set, the kernel will manage legacy INTx interrupts1337 guest's view on the INTx mask, see KVM_ASSIGN_SET_INTX_MASK for details.1676 Allows userspace to mask PCI INTx interrupts from the assigned device. The1677 kernel will not deliver INTx interrupts to the guest between setting and1679 and emulation of PCI 2.3 INTx disable command register behavior.1681 This may be used for both PCI 2.3 devices supporting INTx disable natively and1683 read value of the INTx disable bit in the guest visible PCI command register.1684 When modifying the INTx disable state, userspace should precede updating the1686 the new intended INTx mask state.1688 Note that the kernel uses the device INTx disable bit to internally manage the[all …]
170 INTx emulation mode. Since service drivers of the same PCI-PCI Bridge
475 INTx, enumerator
8590 phba->intr_type = INTx; in lpfc_sli_enable_intr()8614 else if (phba->intr_type == INTx) in lpfc_sli_disable_intr()9161 phba->intr_type = INTx; in lpfc_sli4_enable_intr()9198 else if (phba->intr_type == INTx) in lpfc_sli4_disable_intr()
347 if ((q->phba->intr_type == INTx) && (arm == LPFC_QUEUE_REARM)) in lpfc_sli4_eq_release()
2892 makes all PCIe ports use INTx for hotplug services).2905 all PCIe root ports use INTx for all services).
944 Some chipsets generate a legacy INTx "boot IRQ" when the IRQ