Searched refs:IMX6QDL_CLK_PLL5_POST_DIV (Results 1 - 8 of 8) sorted by relevance

/linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/clock/
H A Dimx6qdl-clock.h207 #define IMX6QDL_CLK_PLL5_POST_DIV 194 macro
/linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/clock/
H A Dimx6qdl-clock.h207 #define IMX6QDL_CLK_PLL5_POST_DIV 194 macro
/linux-4.4.14/include/dt-bindings/clock/
H A Dimx6qdl-clock.h207 #define IMX6QDL_CLK_PLL5_POST_DIV 194 macro
/linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/clock/
H A Dimx6qdl-clock.h207 #define IMX6QDL_CLK_PLL5_POST_DIV 194 macro
/linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/clock/
H A Dimx6qdl-clock.h207 #define IMX6QDL_CLK_PLL5_POST_DIV 194 macro
/linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/clock/
H A Dimx6qdl-clock.h207 #define IMX6QDL_CLK_PLL5_POST_DIV 194 macro
/linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/clock/
H A Dimx6qdl-clock.h207 #define IMX6QDL_CLK_PLL5_POST_DIV 194 macro
/linux-4.4.14/drivers/clk/imx/
H A Dclk-imx6q.c274 clk[IMX6QDL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6q_clocks_init()

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