| /linux-4.4.14/drivers/isdn/hisax/ |
| H A D | hfcscard.c | 30 (stat = cs->BC_Read_Reg(cs, HFCD_DATA, HFCD_STAT))) { hfcs_interrupt()
31 val = cs->BC_Read_Reg(cs, HFCD_DATA, HFCD_INT_S1); hfcs_interrupt()
48 /* WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcD.ctmt | 0x80); hfcs_Timer()
69 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CIRM, cs->hw.hfcD.cirm); /* Reset On */ reset_hfcs()
74 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CIRM, cs->hw.hfcD.cirm); /* Reset Off */ reset_hfcs()
80 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CIRM, cs->hw.hfcD.cirm); reset_hfcs()
81 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CLKDEL, 0x0e); reset_hfcs()
82 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_TEST, HFCD_AUTO_AWAKE); /* S/T Auto awake */ reset_hfcs()
84 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcD.ctmt); reset_hfcs()
89 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_INT_M1, cs->hw.hfcD.int_m1); reset_hfcs()
90 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_INT_M2, cs->hw.hfcD.int_m2); reset_hfcs()
91 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_STATES, HFCD_LOAD_STATE | 2); /* HFC ST 2 */ reset_hfcs()
93 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_STATES, 2); /* HFC ST 2 */ reset_hfcs()
95 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_MST_MODE, cs->hw.hfcD.mst_m); /* HFC Master */ reset_hfcs()
97 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_SCTRL, cs->hw.hfcD.sctrl); reset_hfcs()
128 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcD.ctmt); hfcs_card_msg()
129 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_MST_MODE, cs->hw.hfcD.mst_m); hfcs_card_msg()
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| H A D | hfc_2bds0.c | 74 return (ReadReg(cs, HFCD_DATA, offset)); readreghfcd()
80 WriteReg(cs, HFCD_DATA, offset, value); writereghfcd()
88 while (!(ReadReg(cs, HFCD_DATA, HFCD_STAT) & HFCD_BUSY) && to) { WaitForBusy()
137 cs->BC_Write_Reg(cs, HFCD_DATA, cip, 0); SelFiFo()
176 val = 256 * ReadReg(cs, HFCD_DATA, reg | HFCB_Z_HIGH); ReadZReg()
178 val += ReadReg(cs, HFCD_DATA, reg | HFCB_Z_LOW); ReadZReg()
234 chksum = (ReadReg(cs, HFCD_DATA, cip) << 8); hfc_empty_fifo()
236 chksum += ReadReg(cs, HFCD_DATA, cip); hfc_empty_fifo()
238 stat = ReadReg(cs, HFCD_DATA, cip); hfc_empty_fifo()
254 stat = ReadReg(cs, HFCD_DATA, HFCB_FIFO | HFCB_F2_INC | hfc_empty_fifo()
275 bcs->hw.hfc.f1 = ReadReg(cs, HFCD_DATA, cip); hfc_fill_fifo()
279 bcs->hw.hfc.f2 = ReadReg(cs, HFCD_DATA, cip); hfc_fill_fifo()
332 ReadReg(cs, HFCD_DATA, HFCB_FIFO | HFCB_F1_INC | HFCB_SEND | HFCB_CHANNEL(bcs->channel)); hfc_fill_fifo()
368 f1 = ReadReg(cs, HFCD_DATA, cip); main_rec_2bds0()
371 f2 = ReadReg(cs, HFCD_DATA, cip); main_rec_2bds0()
447 WriteReg(cs, HFCD_DATA, HFCD_SCTRL, cs->hw.hfcD.sctrl); mode_2bs0()
448 WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcD.ctmt); mode_2bs0()
449 WriteReg(cs, HFCD_DATA, HFCD_CONN, cs->hw.hfcD.conn); mode_2bs0()
653 chksum = (ReadReg(cs, HFCD_DATA, cip) << 8); receive_dmsg()
655 chksum += ReadReg(cs, HFCD_DATA, cip); receive_dmsg()
657 stat = ReadReg(cs, HFCD_DATA, cip); receive_dmsg()
678 stat = ReadReg(cs, HFCD_DATA, cip); receive_dmsg()
703 cs->hw.hfcD.f1 = ReadReg(cs, HFCD_DATA, cip) & 0xf; hfc_fill_dfifo()
706 cs->hw.hfcD.f2 = ReadReg(cs, HFCD_DATA, cip) & 0xf; hfc_fill_dfifo()
746 ReadReg(cs, HFCD_DATA, HFCD_FIFO | HFCD_F1_INC | HFCD_SEND); hfc_fill_dfifo()
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| H A D | hfc_2bds0.h | 60 #define HFCD_DATA 1 macro
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| H A D | hfc_sx.c | 425 /* WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcsx.ctmt | 0x80); hfcsx_Timer()
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| H A D | hfc_pci.c | 172 /* WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcpci.ctmt | 0x80); hfcpci_Timer()
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| /linux-4.4.14/drivers/isdn/hardware/mISDN/ |
| H A D | hfcpci.c | 309 * WriteReg(hc, HFCD_DATA, HFCD_CTMT, hc->hw.ctmt | 0x80); hfcpci_Timer()
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