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Searched refs:HDMI_CORE_BASE (Results 1 - 2 of 2) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/exynos/
H A D	regs-hdmi.h	24 #define HDMI_CORE_BASE(x) ((x) + 0x00010000) macro 38 #define HDMI_CON_0 HDMI_CORE_BASE(0x0000) 39 #define HDMI_CON_1 HDMI_CORE_BASE(0x0004) 40 #define HDMI_CON_2 HDMI_CORE_BASE(0x0008) 41 #define HDMI_SYS_STATUS HDMI_CORE_BASE(0x0010) 42 #define HDMI_V13_PHY_STATUS HDMI_CORE_BASE(0x0014) 43 #define HDMI_STATUS_EN HDMI_CORE_BASE(0x0020) 44 #define HDMI_HPD HDMI_CORE_BASE(0x0030) 45 #define HDMI_MODE_SEL HDMI_CORE_BASE(0x0040) 46 #define HDMI_ENC_EN HDMI_CORE_BASE(0x0044) 47 #define HDMI_V13_BLUE_SCREEN_0 HDMI_CORE_BASE(0x0050) 48 #define HDMI_V13_BLUE_SCREEN_1 HDMI_CORE_BASE(0x0054) 49 #define HDMI_V13_BLUE_SCREEN_2 HDMI_CORE_BASE(0x0058) 50 #define HDMI_H_BLANK_0 HDMI_CORE_BASE(0x00A0) 51 #define HDMI_H_BLANK_1 HDMI_CORE_BASE(0x00A4) 52 #define HDMI_V13_V_BLANK_0 HDMI_CORE_BASE(0x00B0) 53 #define HDMI_V13_V_BLANK_1 HDMI_CORE_BASE(0x00B4) 54 #define HDMI_V13_V_BLANK_2 HDMI_CORE_BASE(0x00B8) 55 #define HDMI_V13_H_V_LINE_0 HDMI_CORE_BASE(0x00C0) 56 #define HDMI_V13_H_V_LINE_1 HDMI_CORE_BASE(0x00C4) 57 #define HDMI_V13_H_V_LINE_2 HDMI_CORE_BASE(0x00C8) 58 #define HDMI_VSYNC_POL HDMI_CORE_BASE(0x00E4) 59 #define HDMI_INT_PRO_MODE HDMI_CORE_BASE(0x00E8) 60 #define HDMI_V13_V_BLANK_F_0 HDMI_CORE_BASE(0x0110) 61 #define HDMI_V13_V_BLANK_F_1 HDMI_CORE_BASE(0x0114) 62 #define HDMI_V13_V_BLANK_F_2 HDMI_CORE_BASE(0x0118) 63 #define HDMI_V13_H_SYNC_GEN_0 HDMI_CORE_BASE(0x0120) 64 #define HDMI_V13_H_SYNC_GEN_1 HDMI_CORE_BASE(0x0124) 65 #define HDMI_V13_H_SYNC_GEN_2 HDMI_CORE_BASE(0x0128) 66 #define HDMI_V13_V_SYNC_GEN_1_0 HDMI_CORE_BASE(0x0130) 67 #define HDMI_V13_V_SYNC_GEN_1_1 HDMI_CORE_BASE(0x0134) 68 #define HDMI_V13_V_SYNC_GEN_1_2 HDMI_CORE_BASE(0x0138) 69 #define HDMI_V13_V_SYNC_GEN_2_0 HDMI_CORE_BASE(0x0140) 70 #define HDMI_V13_V_SYNC_GEN_2_1 HDMI_CORE_BASE(0x0144) 71 #define HDMI_V13_V_SYNC_GEN_2_2 HDMI_CORE_BASE(0x0148) 72 #define HDMI_V13_V_SYNC_GEN_3_0 HDMI_CORE_BASE(0x0150) 73 #define HDMI_V13_V_SYNC_GEN_3_1 HDMI_CORE_BASE(0x0154) 74 #define HDMI_V13_V_SYNC_GEN_3_2 HDMI_CORE_BASE(0x0158) 75 #define HDMI_V13_AVI_CON HDMI_CORE_BASE(0x0300) 76 #define HDMI_V13_AVI_BYTE(n) HDMI_CORE_BASE(0x0320 + 4 * (n)) 77 #define HDMI_V13_DC_CONTROL HDMI_CORE_BASE(0x05C0) 78 #define HDMI_V13_VIDEO_PATTERN_GEN HDMI_CORE_BASE(0x05C4) 79 #define HDMI_V13_HPD_GEN HDMI_CORE_BASE(0x05C8) 80 #define HDMI_V13_AUI_CON HDMI_CORE_BASE(0x0360) 81 #define HDMI_V13_SPD_CON HDMI_CORE_BASE(0x0400) 184 #define HDMI_YMAX HDMI_CORE_BASE(0x0060) 185 #define HDMI_YMIN HDMI_CORE_BASE(0x0064) 186 #define HDMI_CMAX HDMI_CORE_BASE(0x0068) 187 #define HDMI_CMIN HDMI_CORE_BASE(0x006C) 189 #define HDMI_V2_BLANK_0 HDMI_CORE_BASE(0x00B0) 190 #define HDMI_V2_BLANK_1 HDMI_CORE_BASE(0x00B4) 191 #define HDMI_V1_BLANK_0 HDMI_CORE_BASE(0x00B8) 192 #define HDMI_V1_BLANK_1 HDMI_CORE_BASE(0x00BC) 194 #define HDMI_V_LINE_0 HDMI_CORE_BASE(0x00C0) 195 #define HDMI_V_LINE_1 HDMI_CORE_BASE(0x00C4) 196 #define HDMI_H_LINE_0 HDMI_CORE_BASE(0x00C8) 197 #define HDMI_H_LINE_1 HDMI_CORE_BASE(0x00CC) 199 #define HDMI_HSYNC_POL HDMI_CORE_BASE(0x00E0) 201 #define HDMI_V_BLANK_F0_0 HDMI_CORE_BASE(0x0110) 202 #define HDMI_V_BLANK_F0_1 HDMI_CORE_BASE(0x0114) 203 #define HDMI_V_BLANK_F1_0 HDMI_CORE_BASE(0x0118) 204 #define HDMI_V_BLANK_F1_1 HDMI_CORE_BASE(0x011C) 206 #define HDMI_H_SYNC_START_0 HDMI_CORE_BASE(0x0120) 207 #define HDMI_H_SYNC_START_1 HDMI_CORE_BASE(0x0124) 208 #define HDMI_H_SYNC_END_0 HDMI_CORE_BASE(0x0128) 209 #define HDMI_H_SYNC_END_1 HDMI_CORE_BASE(0x012C) 211 #define HDMI_V_SYNC_LINE_BEF_2_0 HDMI_CORE_BASE(0x0130) 212 #define HDMI_V_SYNC_LINE_BEF_2_1 HDMI_CORE_BASE(0x0134) 213 #define HDMI_V_SYNC_LINE_BEF_1_0 HDMI_CORE_BASE(0x0138) 214 #define HDMI_V_SYNC_LINE_BEF_1_1 HDMI_CORE_BASE(0x013C) 216 #define HDMI_V_SYNC_LINE_AFT_2_0 HDMI_CORE_BASE(0x0140) 217 #define HDMI_V_SYNC_LINE_AFT_2_1 HDMI_CORE_BASE(0x0144) 218 #define HDMI_V_SYNC_LINE_AFT_1_0 HDMI_CORE_BASE(0x0148) 219 #define HDMI_V_SYNC_LINE_AFT_1_1 HDMI_CORE_BASE(0x014C) 221 #define HDMI_V_SYNC_LINE_AFT_PXL_2_0 HDMI_CORE_BASE(0x0150) 222 #define HDMI_V_SYNC_LINE_AFT_PXL_2_1 HDMI_CORE_BASE(0x0154) 223 #define HDMI_V_SYNC_LINE_AFT_PXL_1_0 HDMI_CORE_BASE(0x0158) 224 #define HDMI_V_SYNC_LINE_AFT_PXL_1_1 HDMI_CORE_BASE(0x015C) 226 #define HDMI_V_BLANK_F2_0 HDMI_CORE_BASE(0x0160) 227 #define HDMI_V_BLANK_F2_1 HDMI_CORE_BASE(0x0164) 228 #define HDMI_V_BLANK_F3_0 HDMI_CORE_BASE(0x0168) 229 #define HDMI_V_BLANK_F3_1 HDMI_CORE_BASE(0x016C) 230 #define HDMI_V_BLANK_F4_0 HDMI_CORE_BASE(0x0170) 231 #define HDMI_V_BLANK_F4_1 HDMI_CORE_BASE(0x0174) 232 #define HDMI_V_BLANK_F5_0 HDMI_CORE_BASE(0x0178) 233 #define HDMI_V_BLANK_F5_1 HDMI_CORE_BASE(0x017C) 235 #define HDMI_V_SYNC_LINE_AFT_3_0 HDMI_CORE_BASE(0x0180) 236 #define HDMI_V_SYNC_LINE_AFT_3_1 HDMI_CORE_BASE(0x0184) 237 #define HDMI_V_SYNC_LINE_AFT_4_0 HDMI_CORE_BASE(0x0188) 238 #define HDMI_V_SYNC_LINE_AFT_4_1 HDMI_CORE_BASE(0x018C) 239 #define HDMI_V_SYNC_LINE_AFT_5_0 HDMI_CORE_BASE(0x0190) 240 #define HDMI_V_SYNC_LINE_AFT_5_1 HDMI_CORE_BASE(0x0194) 241 #define HDMI_V_SYNC_LINE_AFT_6_0 HDMI_CORE_BASE(0x0198) 242 #define HDMI_V_SYNC_LINE_AFT_6_1 HDMI_CORE_BASE(0x019C) 244 #define HDMI_V_SYNC_LINE_AFT_PXL_3_0 HDMI_CORE_BASE(0x01A0) 245 #define HDMI_V_SYNC_LINE_AFT_PXL_3_1 HDMI_CORE_BASE(0x01A4) 246 #define HDMI_V_SYNC_LINE_AFT_PXL_4_0 HDMI_CORE_BASE(0x01A8) 247 #define HDMI_V_SYNC_LINE_AFT_PXL_4_1 HDMI_CORE_BASE(0x01AC) 248 #define HDMI_V_SYNC_LINE_AFT_PXL_5_0 HDMI_CORE_BASE(0x01B0) 249 #define HDMI_V_SYNC_LINE_AFT_PXL_5_1 HDMI_CORE_BASE(0x01B4) 250 #define HDMI_V_SYNC_LINE_AFT_PXL_6_0 HDMI_CORE_BASE(0x01B8) 251 #define HDMI_V_SYNC_LINE_AFT_PXL_6_1 HDMI_CORE_BASE(0x01BC) 253 #define HDMI_VACT_SPACE_1_0 HDMI_CORE_BASE(0x01C0) 254 #define HDMI_VACT_SPACE_1_1 HDMI_CORE_BASE(0x01C4) 255 #define HDMI_VACT_SPACE_2_0 HDMI_CORE_BASE(0x01C8) 256 #define HDMI_VACT_SPACE_2_1 HDMI_CORE_BASE(0x01CC) 257 #define HDMI_VACT_SPACE_3_0 HDMI_CORE_BASE(0x01D0) 258 #define HDMI_VACT_SPACE_3_1 HDMI_CORE_BASE(0x01D4) 259 #define HDMI_VACT_SPACE_4_0 HDMI_CORE_BASE(0x01D8) 260 #define HDMI_VACT_SPACE_4_1 HDMI_CORE_BASE(0x01DC) 261 #define HDMI_VACT_SPACE_5_0 HDMI_CORE_BASE(0x01E0) 262 #define HDMI_VACT_SPACE_5_1 HDMI_CORE_BASE(0x01E4) 263 #define HDMI_VACT_SPACE_6_0 HDMI_CORE_BASE(0x01E8) 264 #define HDMI_VACT_SPACE_6_1 HDMI_CORE_BASE(0x01EC) 266 #define HDMI_GCP_CON HDMI_CORE_BASE(0x0200) 267 #define HDMI_GCP_BYTE1 HDMI_CORE_BASE(0x0210) 268 #define HDMI_GCP_BYTE2 HDMI_CORE_BASE(0x0214) 269 #define HDMI_GCP_BYTE3 HDMI_CORE_BASE(0x0218) 272 #define HDMI_ASP_CON HDMI_CORE_BASE(0x0300) 273 #define HDMI_ASP_SP_FLAT HDMI_CORE_BASE(0x0304) 274 #define HDMI_ASP_CHCFG0 HDMI_CORE_BASE(0x0310) 275 #define HDMI_ASP_CHCFG1 HDMI_CORE_BASE(0x0314) 276 #define HDMI_ASP_CHCFG2 HDMI_CORE_BASE(0x0318) 277 #define HDMI_ASP_CHCFG3 HDMI_CORE_BASE(0x031C) 279 #define HDMI_V13_ACR_CON HDMI_CORE_BASE(0x0180) 280 #define HDMI_V13_ACR_MCTS0 HDMI_CORE_BASE(0x0184) 281 #define HDMI_V13_ACR_MCTS1 HDMI_CORE_BASE(0x0188) 282 #define HDMI_V13_ACR_MCTS2 HDMI_CORE_BASE(0x018C) 283 #define HDMI_V13_ACR_CTS0 HDMI_CORE_BASE(0x0190) 284 #define HDMI_V13_ACR_CTS1 HDMI_CORE_BASE(0x0194) 285 #define HDMI_V13_ACR_CTS2 HDMI_CORE_BASE(0x0198) 286 #define HDMI_V13_ACR_N0 HDMI_CORE_BASE(0x01A0) 287 #define HDMI_V13_ACR_N1 HDMI_CORE_BASE(0x01A4) 288 #define HDMI_V13_ACR_N2 HDMI_CORE_BASE(0x01A8) 289 #define HDMI_V14_ACR_CON HDMI_CORE_BASE(0x0400) 290 #define HDMI_V14_ACR_MCTS0 HDMI_CORE_BASE(0x0410) 291 #define HDMI_V14_ACR_MCTS1 HDMI_CORE_BASE(0x0414) 292 #define HDMI_V14_ACR_MCTS2 HDMI_CORE_BASE(0x0418) 293 #define HDMI_V14_ACR_CTS0 HDMI_CORE_BASE(0x0420) 294 #define HDMI_V14_ACR_CTS1 HDMI_CORE_BASE(0x0424) 295 #define HDMI_V14_ACR_CTS2 HDMI_CORE_BASE(0x0428) 296 #define HDMI_V14_ACR_N0 HDMI_CORE_BASE(0x0430) 297 #define HDMI_V14_ACR_N1 HDMI_CORE_BASE(0x0434) 298 #define HDMI_V14_ACR_N2 HDMI_CORE_BASE(0x0438) 301 #define HDMI_ACP_CON HDMI_CORE_BASE(0x0500) 302 #define HDMI_ACP_TYPE HDMI_CORE_BASE(0x0514) 303 #define HDMI_ACP_DATA(n) HDMI_CORE_BASE(0x0520 + 4 * (n)) 305 #define HDMI_ISRC_CON HDMI_CORE_BASE(0x0600) 306 #define HDMI_ISRC1_HEADER1 HDMI_CORE_BASE(0x0614) 307 #define HDMI_ISRC1_DATA(n) HDMI_CORE_BASE(0x0620 + 4 * (n)) 308 #define HDMI_ISRC2_DATA(n) HDMI_CORE_BASE(0x06A0 + 4 * (n)) 310 #define HDMI_AVI_CON HDMI_CORE_BASE(0x0700) 311 #define HDMI_AVI_HEADER0 HDMI_CORE_BASE(0x0710) 312 #define HDMI_AVI_HEADER1 HDMI_CORE_BASE(0x0714) 313 #define HDMI_AVI_HEADER2 HDMI_CORE_BASE(0x0718) 314 #define HDMI_AVI_CHECK_SUM HDMI_CORE_BASE(0x071C) 315 #define HDMI_AVI_BYTE(n) HDMI_CORE_BASE(0x0720 + 4 * (n-1)) 317 #define HDMI_AUI_CON HDMI_CORE_BASE(0x0800) 318 #define HDMI_AUI_HEADER0 HDMI_CORE_BASE(0x0810) 319 #define HDMI_AUI_HEADER1 HDMI_CORE_BASE(0x0814) 320 #define HDMI_AUI_HEADER2 HDMI_CORE_BASE(0x0818) 321 #define HDMI_AUI_CHECK_SUM HDMI_CORE_BASE(0x081C) 322 #define HDMI_AUI_BYTE(n) HDMI_CORE_BASE(0x0820 + 4 * (n-1)) 324 #define HDMI_MPG_CON HDMI_CORE_BASE(0x0900) 325 #define HDMI_MPG_CHECK_SUM HDMI_CORE_BASE(0x091C) 326 #define HDMI_MPG_DATA(n) HDMI_CORE_BASE(0x0920 + 4 * (n)) 328 #define HDMI_SPD_CON HDMI_CORE_BASE(0x0A00) 329 #define HDMI_SPD_HEADER0 HDMI_CORE_BASE(0x0A10) 330 #define HDMI_SPD_HEADER1 HDMI_CORE_BASE(0x0A14) 331 #define HDMI_SPD_HEADER2 HDMI_CORE_BASE(0x0A18) 332 #define HDMI_SPD_DATA(n) HDMI_CORE_BASE(0x0A20 + 4 * (n)) 334 #define HDMI_GAMUT_CON HDMI_CORE_BASE(0x0B00) 335 #define HDMI_GAMUT_HEADER0 HDMI_CORE_BASE(0x0B10) 336 #define HDMI_GAMUT_HEADER1 HDMI_CORE_BASE(0x0B14) 337 #define HDMI_GAMUT_HEADER2 HDMI_CORE_BASE(0x0B18) 338 #define HDMI_GAMUT_METADATA(n) HDMI_CORE_BASE(0x0B20 + 4 * (n)) 340 #define HDMI_VSI_CON HDMI_CORE_BASE(0x0C00) 341 #define HDMI_VSI_HEADER0 HDMI_CORE_BASE(0x0C10) 342 #define HDMI_VSI_HEADER1 HDMI_CORE_BASE(0x0C14) 343 #define HDMI_VSI_HEADER2 HDMI_CORE_BASE(0x0C18) 344 #define HDMI_VSI_DATA(n) HDMI_CORE_BASE(0x0C20 + 4 * (n)) 346 #define HDMI_DC_CONTROL HDMI_CORE_BASE(0x0D00) 347 #define HDMI_VIDEO_PATTERN_GEN HDMI_CORE_BASE(0x0D04) 349 #define HDMI_AN_SEED_SEL HDMI_CORE_BASE(0x0E48) 350 #define HDMI_AN_SEED_0 HDMI_CORE_BASE(0x0E58) 351 #define HDMI_AN_SEED_1 HDMI_CORE_BASE(0x0E5C) 352 #define HDMI_AN_SEED_2 HDMI_CORE_BASE(0x0E60) 353 #define HDMI_AN_SEED_3 HDMI_CORE_BASE(0x0E64) 369 #define HDMI_HDCP_SHA1(n) HDMI_CORE_BASE(0x7000 + 4 * (n)) 370 #define HDMI_HDCP_KSV_LIST(n) HDMI_CORE_BASE(0x7050 + 4 * (n)) 372 #define HDMI_HDCP_KSV_LIST_CON HDMI_CORE_BASE(0x7064) 373 #define HDMI_HDCP_SHA_RESULT HDMI_CORE_BASE(0x7070) 374 #define HDMI_HDCP_CTRL1 HDMI_CORE_BASE(0x7080) 375 #define HDMI_HDCP_CTRL2 HDMI_CORE_BASE(0x7084) 376 #define HDMI_HDCP_CHECK_RESULT HDMI_CORE_BASE(0x7090) 377 #define HDMI_HDCP_BKSV(n) HDMI_CORE_BASE(0x70A0 + 4 * (n)) 378 #define HDMI_HDCP_AKSV(n) HDMI_CORE_BASE(0x70C0 + 4 * (n)) 379 #define HDMI_HDCP_AN(n) HDMI_CORE_BASE(0x70E0 + 4 * (n)) 381 #define HDMI_HDCP_BCAPS HDMI_CORE_BASE(0x7100) 382 #define HDMI_HDCP_BSTATUS_0 HDMI_CORE_BASE(0x7110) 383 #define HDMI_HDCP_BSTATUS_1 HDMI_CORE_BASE(0x7114) 384 #define HDMI_HDCP_RI_0 HDMI_CORE_BASE(0x7140) 385 #define HDMI_HDCP_RI_1 HDMI_CORE_BASE(0x7144) 386 #define HDMI_HDCP_I2C_INT HDMI_CORE_BASE(0x7180) 387 #define HDMI_HDCP_AN_INT HDMI_CORE_BASE(0x7190) 388 #define HDMI_HDCP_WDT_INT HDMI_CORE_BASE(0x71A0) 389 #define HDMI_HDCP_RI_INT HDMI_CORE_BASE(0x71B0) 390 #define HDMI_HDCP_RI_COMPARE_0 HDMI_CORE_BASE(0x71D0) 391 #define HDMI_HDCP_RI_COMPARE_1 HDMI_CORE_BASE(0x71D4) 392 #define HDMI_HDCP_FRAME_COUNT HDMI_CORE_BASE(0x71E0) 394 #define HDMI_RGB_ROUND_EN HDMI_CORE_BASE(0xD500) 395 #define HDMI_VACT_SPACE_R_0 HDMI_CORE_BASE(0xD504) 396 #define HDMI_VACT_SPACE_R_1 HDMI_CORE_BASE(0xD508) 397 #define HDMI_VACT_SPACE_G_0 HDMI_CORE_BASE(0xD50C) 398 #define HDMI_VACT_SPACE_G_1 HDMI_CORE_BASE(0xD510) 399 #define HDMI_VACT_SPACE_B_0 HDMI_CORE_BASE(0xD514) 400 #define HDMI_VACT_SPACE_B_1 HDMI_CORE_BASE(0xD518) 402 #define HDMI_BLUE_SCREEN_B_0 HDMI_CORE_BASE(0xD520) 403 #define HDMI_BLUE_SCREEN_B_1 HDMI_CORE_BASE(0xD524) 404 #define HDMI_BLUE_SCREEN_G_0 HDMI_CORE_BASE(0xD528) 405 #define HDMI_BLUE_SCREEN_G_1 HDMI_CORE_BASE(0xD52C) 406 #define HDMI_BLUE_SCREEN_R_0 HDMI_CORE_BASE(0xD530) 407 #define HDMI_BLUE_SCREEN_R_1 HDMI_CORE_BASE(0xD534)
/linux-4.4.14/drivers/media/platform/s5p-tv/
H A D	regs-hdmi.h	21 #define HDMI_CORE_BASE(x) ((x) + 0x00010000) macro 34 #define HDMI_CON_0 HDMI_CORE_BASE(0x0000) 35 #define HDMI_CON_1 HDMI_CORE_BASE(0x0004) 36 #define HDMI_CON_2 HDMI_CORE_BASE(0x0008) 37 #define HDMI_SYS_STATUS HDMI_CORE_BASE(0x0010) 38 #define HDMI_PHY_STATUS HDMI_CORE_BASE(0x0014) 39 #define HDMI_STATUS_EN HDMI_CORE_BASE(0x0020) 40 #define HDMI_HPD HDMI_CORE_BASE(0x0030) 41 #define HDMI_MODE_SEL HDMI_CORE_BASE(0x0040) 42 #define HDMI_BLUE_SCREEN_0 HDMI_CORE_BASE(0x0050) 43 #define HDMI_BLUE_SCREEN_1 HDMI_CORE_BASE(0x0054) 44 #define HDMI_BLUE_SCREEN_2 HDMI_CORE_BASE(0x0058) 45 #define HDMI_H_BLANK_0 HDMI_CORE_BASE(0x00A0) 46 #define HDMI_H_BLANK_1 HDMI_CORE_BASE(0x00A4) 47 #define HDMI_V_BLANK_0 HDMI_CORE_BASE(0x00B0) 48 #define HDMI_V_BLANK_1 HDMI_CORE_BASE(0x00B4) 49 #define HDMI_V_BLANK_2 HDMI_CORE_BASE(0x00B8) 50 #define HDMI_H_V_LINE_0 HDMI_CORE_BASE(0x00C0) 51 #define HDMI_H_V_LINE_1 HDMI_CORE_BASE(0x00C4) 52 #define HDMI_H_V_LINE_2 HDMI_CORE_BASE(0x00C8) 53 #define HDMI_VSYNC_POL HDMI_CORE_BASE(0x00E4) 54 #define HDMI_INT_PRO_MODE HDMI_CORE_BASE(0x00E8) 55 #define HDMI_V_BLANK_F_0 HDMI_CORE_BASE(0x0110) 56 #define HDMI_V_BLANK_F_1 HDMI_CORE_BASE(0x0114) 57 #define HDMI_V_BLANK_F_2 HDMI_CORE_BASE(0x0118) 58 #define HDMI_H_SYNC_GEN_0 HDMI_CORE_BASE(0x0120) 59 #define HDMI_H_SYNC_GEN_1 HDMI_CORE_BASE(0x0124) 60 #define HDMI_H_SYNC_GEN_2 HDMI_CORE_BASE(0x0128) 61 #define HDMI_V_SYNC_GEN_1_0 HDMI_CORE_BASE(0x0130) 62 #define HDMI_V_SYNC_GEN_1_1 HDMI_CORE_BASE(0x0134) 63 #define HDMI_V_SYNC_GEN_1_2 HDMI_CORE_BASE(0x0138) 64 #define HDMI_V_SYNC_GEN_2_0 HDMI_CORE_BASE(0x0140) 65 #define HDMI_V_SYNC_GEN_2_1 HDMI_CORE_BASE(0x0144) 66 #define HDMI_V_SYNC_GEN_2_2 HDMI_CORE_BASE(0x0148) 67 #define HDMI_V_SYNC_GEN_3_0 HDMI_CORE_BASE(0x0150) 68 #define HDMI_V_SYNC_GEN_3_1 HDMI_CORE_BASE(0x0154) 69 #define HDMI_V_SYNC_GEN_3_2 HDMI_CORE_BASE(0x0158) 70 #define HDMI_AVI_CON HDMI_CORE_BASE(0x0300) 71 #define HDMI_AVI_BYTE(n) HDMI_CORE_BASE(0x0320 + 4 * (n)) 72 #define HDMI_DC_CONTROL HDMI_CORE_BASE(0x05C0) 73 #define HDMI_VIDEO_PATTERN_GEN HDMI_CORE_BASE(0x05C4) 74 #define HDMI_HPD_GEN HDMI_CORE_BASE(0x05C8)

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