Searched refs:EXYNOS_DP_SYS_CTL_2 (Results 1 – 2 of 2) sorted by relevance
129 writel(0x40, dp->reg_base + EXYNOS_DP_SYS_CTL_2); in exynos_dp_reset()1070 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2); in exynos_dp_init_video()1113 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2); in exynos_dp_is_slave_video_stream_clock_on()1114 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2); in exynos_dp_is_slave_video_stream_clock_on()1116 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2); in exynos_dp_is_slave_video_stream_clock_on()
48 #define EXYNOS_DP_SYS_CTL_2 0x604 macro