Searched refs:EXYNOS_DP_LN1_LINK_TRAINING_CTL (Results 1 – 2 of 2) sorted by relevance
59 #define EXYNOS_DP_LN1_LINK_TRAINING_CTL 0x690 macro
950 reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); in exynos_dp_set_lane1_pre_emphasis()953 writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); in exynos_dp_set_lane1_pre_emphasis()991 writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); in exynos_dp_set_lane1_link_training()1024 reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); in exynos_dp_get_lane1_link_training()