Searched refs:EXYNOS_DP_LN0_LINK_TRAINING_CTL (Results 1 – 2 of 2) sorted by relevance
58 #define EXYNOS_DP_LN0_LINK_TRAINING_CTL 0x68C macro
940 reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); in exynos_dp_set_lane0_pre_emphasis()943 writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); in exynos_dp_set_lane0_pre_emphasis()982 writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); in exynos_dp_set_lane0_link_training()1016 reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); in exynos_dp_get_lane0_link_training()