Searched refs:EXYNOS_4210_UPHYCLK_PHYFSEL_24MHZ (Results 1 – 1 of 1) sorted by relevance
59 #define EXYNOS_4210_UPHYCLK_PHYFSEL_24MHZ (0x3 << 0) macro115 *reg = EXYNOS_4210_UPHYCLK_PHYFSEL_24MHZ; in exynos4210_rate_to_clk()