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Searched refs:ENDCPLB (Results 1 – 12 of 12) sorted by relevance

/linux-4.4.14/arch/blackfin/mach-bf537/include/mach/
Dmem_map.h51 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
57 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
65 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
87 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
94 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
102 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
123 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
130 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
138 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
/linux-4.4.14/arch/blackfin/mach-bf533/include/mach/
Dmem_map.h54 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
60 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
68 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
92 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
99 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
107 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
126 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
131 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
/linux-4.4.14/arch/blackfin/mach-bf518/include/mach/
Dmem_map.h49 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
55 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
63 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
/linux-4.4.14/arch/blackfin/mach-bf527/include/mach/
Dmem_map.h49 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
55 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
63 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
/linux-4.4.14/arch/blackfin/mach-bf538/include/mach/
Dmem_map.h53 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
59 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
67 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
/linux-4.4.14/arch/blackfin/mach-bf609/include/mach/
Dmem_map.h61 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
67 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
75 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
/linux-4.4.14/arch/blackfin/mach-bf548/include/mach/
Dmem_map.h53 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
59 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
67 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
/linux-4.4.14/arch/blackfin/include/asm/
Dcplb.h126 #define _disable_dcplb() _disable_cplb(DMEM_CONTROL, ENDCPLB)
127 #define disable_dcplb() disable_cplb(DMEM_CONTROL, ENDCPLB)
146 #define _enable_dcplb() _enable_cplb(DMEM_CONTROL, ENDCPLB)
147 #define enable_dcplb() enable_cplb(DMEM_CONTROL, ENDCPLB)
Ddef_LPBlackfin.h553 #define ENDCPLB 0x00000002 /* Enable DCPLB */ macro
/linux-4.4.14/arch/blackfin/mach-bf561/include/mach/
Dmem_map.h56 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
62 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
70 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
/linux-4.4.14/arch/blackfin/kernel/
Dcplbinfo.c88 (cdata->mem_control & ENDCPLB ? "en" : "dis"), in cplbinfo_start()
Dsetup.c1357 if ((cpudata->dmemctl & (ENDCPLB | DMC_ENABLE)) != (ENDCPLB | DMC_ENABLE))