Searched refs:EBIU_AMBCTL1 (Results 1 – 17 of 17) sorted by relevance
256 PM_SYS_PUSH(9, EBIU_AMBCTL1)284 PM_SYS_POP(9, EBIU_AMBCTL1)
172 #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ macro
470 #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)471 #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
210 #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ macro
358 #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)359 #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
209 #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ macro
375 #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)376 #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
284 #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ macro
482 #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)483 #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
186 #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ macro
338 #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)339 #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
179 #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ macro
472 #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)473 #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
155 #define EBIU_AMBCTL1 0xffc00a08 /* Asynchronous Memory Bank Control Register… macro
217 #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)218 #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
1195 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are1202 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
882 D32(EBIU_AMBCTL1); in bfin_debug_mmrs_init()