Searched refs:Divider (Results 1 – 14 of 14) sorted by relevance
1 * Core Divider Clock bindings for Marvell MVEBU SoCs11 - reg : must be the register address of Core Divider control register
162 uint8_t Divider; member
258 uint8_t Divider; member
1005 pi->vce_level[i].Divider = (u8)dividers.post_div; in kv_populate_vce_table()1068 pi->samu_level[i].Divider = (u8)dividers.post_div; in kv_populate_samu_table()1127 pi->acp_level[i].Divider = (u8)dividers.post_div; in kv_populate_acp_table()
2814 table->VceLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_vce_level()2847 table->AcpLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_acp_level()2879 table->SamuLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_samu_level()
916 pi->vce_level[i].Divider = (u8)dividers.post_div; in kv_populate_vce_table()979 pi->samu_level[i].Divider = (u8)dividers.post_div; in kv_populate_samu_table()1038 pi->acp_level[i].Divider = (u8)dividers.post_div; in kv_populate_acp_table()
2684 table->VceLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_vce_level()2717 table->AcpLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_acp_level()2749 table->SamuLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_samu_level()
36 4: N-Divider output
189 int Multiplier, Divider, Remainder; in ATIReduceRatio() local192 Divider = *Denominator; in ATIReduceRatio()194 while ((Remainder = Multiplier % Divider)) { in ATIReduceRatio()195 Multiplier = Divider; in ATIReduceRatio()196 Divider = Remainder; in ATIReduceRatio()199 *Numerator /= Divider; in ATIReduceRatio()200 *Denominator /= Divider; in ATIReduceRatio()
479 prompt "Core Clock Divider"500 int "System Clock Divider"512 int "System Clock0 Divider"523 int "System Clock1 Divider"533 int "DDR Clock Divider"
86 Voltage R1 R2 Divider Raw Value
220 bit 6-4 = Divider for clock