Searched refs:Descriptor (Results 1 – 23 of 23) sorted by relevance
12 2nd - Descriptor ring control and status register address space.13 3rd - Descriptor ring command register address space.
17 should be encoded following the SEC's Descriptor Header Dword34 are available. It's a single 32-bit cell. Descriptor type information35 should be encoded following the SEC's Descriptor Header Dword DESC_TYPE
31 equal to the number of Descriptor Controller (DECO) engines in a particular
15 - "ring_csr": Descriptor ring control and status register address space16 - "ring_cmd": Descriptor ring command register address space
9 Controllers in AC97 and I2S mode, and the Descriptor-Based DMA
76 for QMan Frame Queue Descriptor (FQD) and Packed Frame Descriptor Record (PFDR).
9 Write to this node to issue "Get Device Descriptor"
68 HIDIOCGRDESCSIZE: Get Report Descriptor Size71 HIDIOCGRDESC: Get Report Descriptor
13 descriptor RAM. Descriptor RAM is configurable as internal or external memory.39 - Descriptor memory setup region.
17 descriptor RAM. Descriptor RAM is configurable as internal or external memory.
10 3.3 Descriptor management75 3.3 Descriptor management:
247 Valid Range: 1 (use every Tx Descriptor)248 4 (use every 4th Tx Descriptor)250 Default Value: 1 (use every Tx Descriptor)
104 Work Element Descriptor (WED)196 The Work Element Descriptor (WED) is a 64-bit argument
30 int "Descriptor Skip Length in 32 bit longwords"
65 Sub-mailbox Descriptor Data
130 + Descriptor364 - Descriptor can be freed in few ways
8 Descriptor Block) requests that can be stored in the RISC chip
24 bool "ARMv7/v8 Long Descriptor Format"
1040 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /*0x08 */ member
1 GPIO Descriptor Driver Interface
1 GPIO Descriptor Consumer Interface
480 Routine Descriptor offset 0=Pointer to Function481 Routine Descriptor offset 4=Pointer to Table of Contents
2128 Local Descriptor Table (LDT) using the modify_ldt(2) system