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Searched refs:DPLL_VGA_MODE_DIS (Results 1 – 8 of 8) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/gma500/
Dcdv_intel_display.c236 REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS); in cdv_dpll_set_clock_cdv()
673 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
736 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set()
Dpsb_intel_display.c163 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
Dpsb_intel_reg.h244 #define DPLL_VGA_MODE_DIS (1 << 28) macro
Doaktrail_crtc.c531 dpll |= DPLL_VGA_MODE_DIS; in oaktrail_crtc_mode_set()
/linux-4.4.14/drivers/gpu/drm/i915/
Dintel_dsi.c491 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in intel_dsi_pre_enable()
Dintel_runtime_pm.c879 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in vlv_display_power_well_init()
Dintel_display.c1787 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); in i9xx_disable_pll()
1802 val = DPLL_VGA_MODE_DIS; in vlv_disable_pll()
1820 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in chv_disable_pll()
7313 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV; in vlv_compute_dpll()
7420 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | in chv_compute_dpll()
7597 dpll = DPLL_VGA_MODE_DIS; in i9xx_compute_dpll()
7670 dpll = DPLL_VGA_MODE_DIS; in i8xx_compute_dpll()
Di915_reg.h2223 #define DPLL_VGA_MODE_DIS (1 << 28) macro