Searched refs:DPLL_FPA01_P1_POST_DIV_SHIFT (Results 1 – 5 of 5) sorted by relevance
349 DPLL_FPA01_P1_POST_DIV_SHIFT); in psb_intel_crtc_clock_get()365 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; in psb_intel_crtc_clock_get()
889 DPLL_FPA01_P1_POST_DIV_SHIFT); in cdv_intel_crtc_clock_get()909 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; in cdv_intel_crtc_clock_get()
266 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 macro
7619 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()7673 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()7678 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()8884 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ironlake_compute_dpll()10575 DPLL_FPA01_P1_POST_DIV_SHIFT); in i9xx_crtc_clock_get()10602 DPLL_FPA01_P1_POST_DIV_SHIFT); in i9xx_crtc_clock_get()10613 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; in i9xx_crtc_clock_get()
2267 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 macro