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Searched refs:DPIO_PHY0 (Results 1 – 8 of 8) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/i915/
Dintel_runtime_pm.c1008 if (!dev_priv->chv_phy_assert[DPIO_PHY0]) in assert_chv_phy_status()
1009 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | in assert_chv_phy_status()
1010 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | in assert_chv_phy_status()
1011 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | in assert_chv_phy_status()
1012 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | in assert_chv_phy_status()
1013 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | in assert_chv_phy_status()
1014 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); in assert_chv_phy_status()
1022 phy_status |= PHY_POWERGOOD(DPIO_PHY0); in assert_chv_phy_status()
1025 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) in assert_chv_phy_status()
1026 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); in assert_chv_phy_status()
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Dintel_ddi.c2693 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A); in broxton_phy_init()
2694 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) { in broxton_phy_init()
2728 if (phy == DPIO_PHY0) { in broxton_phy_init()
2747 if (phy == DPIO_PHY0) { in broxton_phy_init()
2763 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code); in broxton_phy_init()
2765 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0)); in broxton_phy_init()
2767 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val); in broxton_phy_init()
2779 broxton_phy_init(dev->dev_private, DPIO_PHY0); in broxton_ddi_phy_init()
2797 broxton_phy_uninit(dev_priv, DPIO_PHY0); in broxton_ddi_phy_uninit()
Di915_dma.c849 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; in intel_init_dpio()
852 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; in intel_init_dpio()
Dintel_hdmi.c1704 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); in chv_hdmi_pre_pll_enable()
1978 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); in chv_hdmi_pre_enable()
Dintel_drv.h831 return DPIO_PHY0; in vlv_dport_to_phy()
Dintel_dp.c2890 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); in chv_pre_enable_dp()
2916 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); in chv_dp_pre_pll_enable()
Di915_drv.h168 DPIO_PHY0, enumerator
Di915_reg.h2258 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30))