Searched refs:DMAC0_TC_PER (Results 1 – 7 of 7) sorted by relevance
307 #define DMAC0_TC_PER 0xFFC00B0C /* Traffic control periods */ macro
518 #define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER)519 #define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER,val)
191 #define DMAC0_TC_PER 0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */ macro
482 #define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER)483 #define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER, val)
202 #define DMAC0_TC_PER 0xffc00b0c /* DMA Controller 0 Traffic Control Periods … macro
302 #define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER)303 #define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER, val)
810 D16(DMAC0_TC_PER); in bfin_debug_mmrs_init()