Searched refs:DMA6 (Results 1 - 14 of 14) sorted by relevance

/linux-4.4.14/arch/blackfin/mach-bf538/include/mach/
H A DdefBF539.h97 #define MXVR_DMA6_CONFIG 0xFFC02810 /* MXVR Sync Data DMA6 Config Register */
98 #define MXVR_DMA6_START_ADDR 0xFFC02814 /* MXVR Sync Data DMA6 Start Address Register */
99 #define MXVR_DMA6_COUNT 0xFFC02818 /* MXVR Sync Data DMA6 Loop Count Register */
100 #define MXVR_DMA6_CURR_ADDR 0xFFC0281C /* MXVR Sync Data DMA6 Current Address Register */
101 #define MXVR_DMA6_CURR_COUNT 0xFFC02820 /* MXVR Sync Data DMA6 Current Loop Count Register */
/linux-4.4.14/arch/blackfin/mach-bf548/include/mach/
H A DdefBF549.h110 /* MXVR DMA6 Registers */
112 #define MXVR_DMA6_CONFIG 0xffc02810 /* MXVR Sync Data DMA6 Config Register */
113 #define MXVR_DMA6_START_ADDR 0xffc02814 /* MXVR Sync Data DMA6 Start Address */
114 #define MXVR_DMA6_COUNT 0xffc02818 /* MXVR Sync Data DMA6 Loop Count Register */
115 #define MXVR_DMA6_CURR_ADDR 0xffc0281c /* MXVR Sync Data DMA6 Current Address */
116 #define MXVR_DMA6_CURR_COUNT 0xffc02820 /* MXVR Sync Data DMA6 Current Loop Count */
H A DcdefBF549.h177 /* MXVR DMA6 Registers */
H A Dirq.h28 #define IRQ_UART0_RX BFIN_IRQ(14) /* UART0 RX Interrupt (DMA6) */
H A DdefBF542.h729 #define DMA6_INT 0x40 /* DMA6 pending interrupt */
H A DdefBF547.h1006 #define DMA6_INT 0x40 /* DMA6 pending interrupt */
H A DdefBF54x_base.h1530 #define DMA6 0x4000 /* DMA Channel 6 */ macro
/linux-4.4.14/arch/blackfin/mach-bf533/include/mach/
H A Dirq.h28 #define IRQ_UART0_RX BFIN_IRQ(14) /* DMA6 Interrupt (UART RX) */
/linux-4.4.14/arch/blackfin/mach-bf537/include/mach/
H A Dirq.h22 #define IRQ_SPORT1_TX BFIN_IRQ(8) /* DMA6 Interrupt (SPORT1 TX) */
/linux-4.4.14/arch/blackfin/mach-bf609/include/mach/
H A Dirq.h71 #define IRQ_SPI0_TX BFIN_IRQ(55) /* SPI0 TX Interrupt (DMA6) */
H A DdefBF60x_base.h1644 DMA6
1646 #define DMA6_NEXT_DESC_PTR 0xFFC41300 /* DMA6 Pointer to Next Initial Descriptor */
1647 #define DMA6_START_ADDR 0xFFC41304 /* DMA6 Start Address of Current Buffer */
1648 #define DMA6_CONFIG 0xFFC41308 /* DMA6 Configuration Register */
1649 #define DMA6_X_COUNT 0xFFC4130C /* DMA6 Inner Loop Count Start Value */
1650 #define DMA6_X_MODIFY 0xFFC41310 /* DMA6 Inner Loop Address Increment */
1651 #define DMA6_Y_COUNT 0xFFC41314 /* DMA6 Outer Loop Count Start Value (2D only) */
1652 #define DMA6_Y_MODIFY 0xFFC41318 /* DMA6 Outer Loop Address Increment (2D only) */
1653 #define DMA6_CURR_DESC_PTR 0xFFC41324 /* DMA6 Current Descriptor Pointer */
1654 #define DMA6_PREV_DESC_PTR 0xFFC41328 /* DMA6 Previous Initial Descriptor Pointer */
1655 #define DMA6_CURR_ADDR 0xFFC4132C /* DMA6 Current Address */
1656 #define DMA6_IRQ_STATUS 0xFFC41330 /* DMA6 Status Register */
1657 #define DMA6_CURR_X_COUNT 0xFFC41334 /* DMA6 Current Count(1D) or intra-row XCNT (2D) */
1658 #define DMA6_CURR_Y_COUNT 0xFFC41338 /* DMA6 Current Row Count (2D only) */
1659 #define DMA6_BWL_COUNT 0xFFC41340 /* DMA6 Bandwidth Limit Count */
1660 #define DMA6_CURR_BWL_COUNT 0xFFC41344 /* DMA6 Bandwidth Limit Count Current */
1661 #define DMA6_BWM_COUNT 0xFFC41348 /* DMA6 Bandwidth Monitor Count */
1662 #define DMA6_CURR_BWM_COUNT 0xFFC4134C /* DMA6 Bandwidth Monitor Count Current */
/linux-4.4.14/arch/blackfin/mach-bf527/include/mach/
H A DdefBF525.h643 #define DMA6_INT 0x40 /* DMA6 pending interrupt */
/linux-4.4.14/drivers/tty/serial/
H A Dcrisv10.c229 /* DMA2(ser2), DMA4(ser3), DMA6(ser0) or DMA8(ser1) */
1880 this interrupt is called from DMA2(ser2), DMA4(ser3), DMA6(ser0) or
/linux-4.4.14/drivers/scsi/
H A Deata.c678 drqx : 2; /* DRQ Index (0=DMA0, 1=DMA7, 2=DMA6, 3=DMA5) */

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